Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 64 (14x14) 8-Bit 8.4 MHz I/O number 52

M68HC08

Microcontrollers

freescale.com

MC68HC908AZ60A

MC68HC908AS60A

MC68HC908AZ60E

Data Sheet

MC68HC908AZ60A

Rev. 6

05/2006

Summary of content (414 pages)

PAGE 1
MC68HC908AZ60A MC68HC908AS60A MC68HC908AZ60E Data Sheet M68HC08 Microcontrollers MC68HC908AZ60A Rev. 6 05/2006 freescale.
PAGE 2
PAGE 3
MC68HC908AZ60A MC68HC908AS60A Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2006. All rights reserved.
PAGE 4
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 5
List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 3 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Chapter 4 FLASH-1 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
List of Chapters Chapter 24 Keyboard Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Chapter 25 Timer Interface Module A (TIMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Chapter 26 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 Chapter 27 Byte Data Link Controller (BDLC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.4.9 1.4.10 1.4.11 1.4.12 1.4.13 1.4.14 1.4.15 1.4.16 1.4.17 1.4.18 1.4.19 1.4.20 1.4.21 1.4.22 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 8
Table of Contents Chapter 4 FLASH-1 Memory 4.1 4.2 4.3 4.3.1 4.3.2 4.4 4.5 4.6 4.7 4.8 4.8.1 4.8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH-1 Control and Block Protect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 9
6.5.3 6.5.4 6.5.5 6.6 6.6.1 6.6.2 EEPROM-1 Nonvolatile Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM-1 Timebase Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM-1 Timebase Divider Nonvolatile Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 10
Table of Contents Chapter 9 System Integration Module (SIM) 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 Clock Startup from POR or LVI Reset .
PAGE 11
10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.4.8 10.5 10.5.1 10.5.2 10.5.3 10.6 10.7 10.7.1 10.7.2 10.8 10.9 10.9.1 10.9.2 10.9.3 10.9.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 12
Table of Contents Chapter 14 Monitor ROM (MON) 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.1 Entering Monitor Mode. . . . .
PAGE 13
Chapter 17 External Interrupt Module (IRQ) 17.1 17.2 17.3 17.4 17.5 17.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Pin . . . . . . . . .
PAGE 14
Table of Contents Chapter 19 Serial Peripheral Interface (SPI) 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3 Pin Name and Register Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4 Functional Description . . . . . .
PAGE 15
20.4 20.5 20.5.1 20.5.2 20.6 20.7 20.7.1 20.7.2 20.8 20.8.1 20.8.2 20.8.3 20.8.4 20.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . .
PAGE 16
Table of Contents 22.7 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.7.1 Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.7.2 Data Direction Register F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.8 Port G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 17
23.13.8 23.13.9 23.13.10 23.13.11 23.13.12 23.13.13 MSCAN08 Transmitter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSCAN08 Identifier Acceptance Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSCAN08 Receive Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSCAN08 Transmit Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 18
Table of Contents Chapter 26 Analog-to-Digital Converter (ADC) 26.1 26.2 26.3 26.3.1 26.3.2 26.3.3 26.3.4 26.3.5 26.4 26.5 26.5.1 26.5.2 26.6 26.6.1 26.6.2 26.6.3 26.7 26.7.1 26.7.2 26.7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . .
PAGE 19
27.5.4 Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.5.5 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.5.5.1 4X Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.5.5.2 Receiving a Message in Block Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 20
Table of Contents Appendix A MC68HC908AS60 and MC68HC908AZ60 A.1 Changes from the MC68HC908AS60 and MC68HC908AZ60 (non-A suffix devices) . . . . . . . A.1.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1.2 FLASH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1.2.1 FLASH Architecture . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 21
Chapter 1 General Description 1.1 Introduction The MC68HC908AS60A, MC68HC908AZ60A, and MC68HC908AZ60E are members of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
PAGE 22
General Description • • • • • Master Reset Pin and Power-On Reset 16-Bit, 2-Channel Timer Interface Module (TIMB) (AZ only) 5-Bit Keyboard Interrupt Module (64-Pin QFP only) MSCAN Controller Implements CAN 2.
PAGE 23
COMPUTER OPERATING PROPERLY MODULE MONITOR ROM — 256 BYTES TIMER A 6 CHANNEL INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES TIMER B INTERFACE MODULE OSC1 OSC2 CGMXFC RST IRQ CLOCK GENERATOR MODULE SERIAL COMMUNICATIONS INTERFACE MODULE SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE POWER-ON RESET MODULE VSS VDD VDDA VSSA KEYBOARD INTERRUPT MODULE IRQ MODULE POWER PROGRAMMABLE INTERRUPT TIMER MODULE AVSS/VREFL VDDAREF DDRA PTA DDRB PTB DDRC PTC PTD USER EEPROM — 1024
PAGE 24
DDRA PTA PTB7/ATD7–PTB0/ATD0 PTC5* PTC4 PTC3 PTC2/MCLK PTC1–PTC0 BREAK MODULE USER FLASH — 60 kBYTES DDRC CONTROL AND STATUS REGISTERS — 62 BYTES USER EEPROM — 1024 BYTES COMPUTER OPERATING PROPERLY MODULE MONITOR ROM — 256 BYTES TIMER A 6 CHANNEL INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES PROGRAMMABLE INTERRUPT TIMER MODULE PTD USER RAM — 2048BYTES DDRD LOW-VOLTAGE INHIBIT MODULE PTD7* PTD6/ATD14/TACLK PTD5/ATD13 PTD4/ATD12/TBCLK KEYBOARD INTERRUPT MODULE* POWER-ON RESET MODULE V
PAGE 25
Pin Assignments 1.4 Pin Assignments PTC1 PTC0 OSC1 OSC2 CGMXFC VSSA VDDA VREFH PTD7 PTD6/ATD14/TACLK PTD5/ATD13 PTD4/ATD12/TBCLK 61 60 59 58 57 56 55 54 53 52 51 50 PTC4 1 PTH1/KBD4 PTC2/MCLK 62 49 PTC3 63 64 PTC5 Figure 1-3 shows the MC68HC908AZ60A pin assignments.
PAGE 26
General Description PTC1 PTC0 OSC1 OSC2 CGMXFC VSSA VDDA VREFH PTD7 PTD6/ATD14/TACLK PTD5/ATD13 PTD4/ATD12 61 60 59 58 57 56 55 54 53 52 51 50 PTC4 1 PTH1/KBD4 PTC2/MCLK 62 49 PTC3 63 64 PTC5 Figure 1-4 shows the MC68HC908AS60A 64-pin QFP pin assignments.
PAGE 27
Pin Assignments PTD6/ATD14/TACLK PTD5/ATD13 49 48 PTC4 PTD4/ATD12 VREFH 50 47 VDDA/VDDAREF OSC2 2 51 OSC1 3 VSSA/VREFL PTC0 4 52 PTC1 5 CGMXFC PTC2/MCLK 6 1 PTC3 7 Figure 1-5 shows MC68HC908AS60A 52-pin PLCC pin assignments.
PAGE 28
General Description NOTE The following pin descriptions are just a quick reference. For a more detailed representation, see Chapter 22 Input/Output Ports. 1.4.1 Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as shown in Figure 1-6.
PAGE 29
Pin Assignments 1.4.5 Analog Power Supply Pin (VDDA) VDDA is the power supply pin for the analog portion of the Clock Generator Module (CGM). See Chapter 10 Clock Generator Module (CGM). 1.4.6 Analog Ground Pin (VSSA) VSSA is the ground connection for the analog portion of the Clock Generator Module (CGM). See Chapter 10 Clock Generator Module (CGM). 1.4.7 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the Clock Generator Module (CGM).
PAGE 30
General Description 1.4.15 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) Port E is an 8-bit special function port that shares two of its pins with the Timer Interface Module A (TIMA), four of its pins with the Serial Peripheral Interface module (SPI), and two of its pins with the Serial Communication Interface module (SCI). See Chapter 18 Serial Communications Interface (SCI), Chapter 19 Serial Peripheral Interface (SPI), Chapter 25 Timer Interface Module A (TIMA), and Chapter 22 Input/Output Ports. 1.4.
PAGE 31
Pin Assignments Table 1-1.
PAGE 32
General Description Table 1-1.
PAGE 33
Pin Assignments Table 1-2. Clock Signal Naming Conventions Clock Signal Name Description CGMXCLK Buffered version of OSC1 from Clock Generation Module (CGM) CGMOUT PLL-based or OSC1-based clock output from Clock Generator Module (CGM) Bus Clock CGMOUT divided by two SPSCK SPI serial clock TACLK External clock input for TIMA TBCLK External clock input for TIMB Table 1-3.
PAGE 34
General Description 1.5 Ordering Information This subsection contains instructions for ordering the MC68HC908AZ60A / MC68HC908AS60A. Table 1-4.
PAGE 35
Chapter 2 Memory Map 2.1 Introduction The CPU08 can address 64K bytes of memory space. The memory map, shown in Figure 2-1, includes: • 60K Bytes of FLASH EEPROM • 2048 Bytes of RAM • 1024 Bytes of EEPROM with Protect Option • 52 Bytes of User-Defined Vectors • 256 Bytes of Monitor ROM The following definitions apply to the memory map representation of reserved and unimplemented locations. • Reserved — Accessing a reserved location can have unpredictable effects on MCU operation.
PAGE 36
Memory Map MC68HC908AZ60A MC68HC908AS60A $0000 $0000 I/O REGISTERS 64 BYTES ↓ ↓ $003F $003F $0040 $0040 ↓ ↓ UNIMPLEMENTED 11 BYTES I/O REGISTERS 16 BYTES $004A $004B I/O REGISTERS 5 BYTES $004F $004F $0050 $0050 RAM-1 1024 BYTES ↓ ↓ $044F $044F $0450 ↓ $0450 FLASH-2 176 BYTES $04FF $0500 ↓ CAN CONTROL AND MESSAGE BUFFERS 128 BYTES FLASH-2 432 BYTES ↓ $057F $0580 ↓ FLASH-2 128 BYTES $05FF $05FF $0600 $0600 ↓ EEPROM-2 512 BYTES ↓ $07FF $07FF $0800 ↓ $0800 EEPROM-1 512 B
PAGE 37
Introduction MC68HC908AZ60A MC68HC908AS60A $FE03 SIM BREAK FLAG CONTROL REGISTER (SBFCR) $FE03 $FE04 RESERVED $FE04 $FE05 RESERVED $FE05 $FE06 RESERVED $FE06 $FE07 RESERVED $FE07 $FE08 FLASH-2 CONTROL REGISTER (FL2CR) $FE08 $FE09 CONFIGURATION WRITE-ONCE REGISER (CONFIG-2) $FE09 $FE0A RESERVED $FE0A $FE0B RESERVED $FE0B $FE0C BREAK ADDRESS REGISTER HIGH (BRKH) $FE0C $FE0D BREAK ADDRESS REGISTER LOW (BRKL) $FE0D $FE0E BREAK STATUS AND CONTROL REGISTER (BSCR) $FE0E $FE0F
PAGE 38
Memory Map MC68HC908AZ60A MC68HC908AS60A $FF75 RESERVED $FF75 $FF76 RESERVED $FF76 $FF77 RESERVED $FF77 $FF78 RESERVED $FF78 $FF79 RESERVED $FF79 $FF7A EEPROM-2 EE DIVIDER HIGH REGISTER (EE2DIVH) $FF7A $FF7B EEPROM-2 EE DIVIDER LOW REGISTER (EE2DIVL) $FF7B $FF7C EEPROM-2 EEPROM NONVOLATILE REGISTER (EE2NVR) $FF7C $FF7D EEPROM-2 EEPROM CONTROL REGISTER (EE2CR) $FF7D $FF7E RESERVED $FF7E $FF7F EEPROM-2 EEPROM ARRAY CONFIGURATION REGISTER (EE2ACR) $FF7F $FF80 FLASH-1 BLOCK P
PAGE 39
I/O Section 2.2 I/O Section Addresses $0000–$004F, shown in Figure 2-2, contain the I/O Data, Status, and Control Registers. Addr.
PAGE 40
Memory Map Addr.
PAGE 41
I/O Section Addr.
PAGE 42
Memory Map Addr.
PAGE 43
I/O Section Addr.
PAGE 44
Memory Map 2.3 Additional Status and Control Registers Selected addresses in the range $FE00 to $FFCB contain additional Status and Control registers as shown in Figure 2-3. A noted exception is the COP Control Register (COPCTL) at address $FFFF. Addr.
PAGE 45
Additional Status and Control Registers Addr.
PAGE 46
Memory Map 2.4 Vector Addresses and Priority Addresses in the range $FFCC to $FFFF contain the user-specified vector locations. The vector addresses are shown in Table 2-1. Please note that certain vector addresses differ between the MC68HC908AS60A and the MC68HC908AZ60A as shown in the table. It is recommended that all vector addresses are defined. Table 2-1.
PAGE 47
Vector Addresses and Priority Table 2-1.
PAGE 48
Memory Map MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 49
Chapter 3 Random-Access Memory (RAM) 3.1 Introduction This chapter describes the 2048 bytes of random-access memory (RAM). 3.2 Functional Description Addresses $0050 through $044F and $0A00 through $0DFF are RAM locations. The location of the stack RAM is programmable with the reset stack pointer instruction (RSP). The 16-bit stack pointer allows the stack RAM to be anywhere in the 64K-byte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations.
PAGE 50
Random-Access Memory (RAM) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 51
Chapter 4 FLASH-1 Memory 4.1 Introduction This chapter describes the operation of the embedded FLASH-1 memory. This memory can be read, programmed and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. 4.
PAGE 52
FLASH-1 Memory 4.3 FLASH-1 Control and Block Protect Registers The FLASH-1 array has two registers that control its operation, the FLASH-1 Control Register (FL1CR) and the FLASH-1 Block Protect Register (FL1BPR). 4.3.1 FLASH-1 Control Register The FLASH-1 Control Register (FL1CR) controls FLASH-1 program and erase operations. Address: Read: $FF88 Bit 7 6 5 4 0 0 0 0 0 0 0 Write: Reset: 0 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 = Unimplemented Figure 4-1.
PAGE 53
FLASH-1 Control and Block Protect Registers 4.3.2 FLASH-1 Block Protect Register The FLASH-1 Block Protect Register (FL1BPR) is implemented as a byte within the FLASH-1 memory and therefore can only be written during a FLASH programming sequence. The value in this register determines the starting location of the protected range within the FLASH-1 memory. Address: Read: Write: $FF80 Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Figure 4-2.
PAGE 54
FLASH-1 Memory Decreasing the value in FL1BPR by one increases the protected range by one page (128 bytes). However, programming the block protect register with $FE protects a range twice that size, 256 bytes, in the corresponding array. $FE means that locations $FF00–$FFFF are protected in FLASH-1. The FLASH memory does not exist at some locations. The block protection range configuration is unaffected if FLASH memory does not exist in that range.
PAGE 55
FLASH-1 Mass Erase Operation 4.5 FLASH-1 Mass Erase Operation Use this step-by-step procedure to erase the entire FLASH-1 memory to read as logic 1: 1. Set both the ERASE bit and the MASS bit in the FLASH-1 Control Register (FL1CR). 2. Read the FLASH-1 Block Protect Register (FL1BPR). 3. Write to any FLASH-1 address within the FLASH-1 array with any data. NOTE If the address written to in Step 3 is within address space protected by the FLASH-1 Block Protect Register (FL1BPR), no erase will occur. 4. 5. 6.
PAGE 56
FLASH-1 Memory 4.6 FLASH-1 Page Erase Operation Use this step-by-step procedure to erase a page (128 bytes) of FLASH-1 memory to read as logic 1: 1. Set the ERASE bit and clear the MASS bit in the FLASH-1 Control Register (FL1CR). 2. Read the FLASH-1 Block Protect Register (FL1BPR). 3. Write any data to any FLASH-1 address within the address range of the page (128 byte block) to be erased. 4. Wait for time, tNVS. 5. Set the HVEN bit. 6. Wait for time, tERASE. 7. Clear the ERASE bit. 8.
PAGE 57
FLASH-1 Program Operation 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Write to any FLASH-1 address within the row address range desired with any data. Wait for time, tNVS. Set the HVEN bit. Wait for time, tPGS. Write data byte to the FLASH-1 address to be programmed. Wait for time, t PROG. Repeat step 7 and 8 until all the bytes within the row are programmed. Clear the PGM bit. Wait for time, tNVH. Clear the HVEN bit. Wait for a time, tRCV, after which the memory can be accessed in normal read mode.
PAGE 58
FLASH-1 Memory 1 Algorithm for programming a row (64 bytes) of FLASH memory 2 3 4 5 6 7 8 Set PGM bit Read the FLASH block protect register Write any data to any FLASH address within the row address range desired Wait for a time, tnvs Set HVEN bit Wait for a time, tpgs Write data to the FLASH address to be programmed Wait for a time, tPROG Completed programming this row? Y N NOTE: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address p
PAGE 59
Low-Power Modes 4.8 Low-Power Modes The WAIT and STOP instructions will place the MCU in low power consumption standby modes. 4.8.1 WAIT Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly; however, no memory activity will take place since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH.
PAGE 60
FLASH-1 Memory MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 61
Chapter 5 FLASH-2 Memory 5.1 Introduction This chapter describes the operation of the embedded FLASH-2 memory. This memory can be read, programmed and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. 5.2 Functional Description The FLASH-2 memory is a non-continuos array consisting of a total of 29,616 bytes on the MC68HC908AS60A and 29,488 bytes on the MC68HC908AZ60A.
PAGE 62
FLASH-2 Memory 5.3 FLASH-2 Control and Block Protect Registers The FLASH-2 array has two registers that control its operation, the FLASH-2 Control Register (FL2CR) and the FLASH-2 Block Protect Register (FL2BPR). 5.3.1 FLASH-2 Control Register The FLASH-2 Control Register (FL2CR) controls FLASH-2 program and erase operations. Address: Read: $FE08 Bit 7 6 5 4 0 0 0 0 0 0 0 Write: Reset: 0 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 = Unimplemented Figure 5-1.
PAGE 63
FLASH-2 Control and Block Protect Registers Address: Read: Write: $FF81 Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Figure 5-2. FLASH-2 Block Protect Register (FL2BPR) NOTE The FLASH-2 Block Protect Register (FL2BPR) controls the block protection for the FLASH-2 array. However, FL2BPR is implemented within the FLASH-1 memory array and therefore, the FLASH-1 Control Register (FL1CR) must be used to program/erase FL2BPR.
PAGE 64
FLASH-2 Memory Decreasing the value in FL2BPR by one increases the protected range by one page (128 bytes). However, programming the block protect register with $FE protects a range twice that size, 256 bytes, in the corresponding array. $FE means that locations $7F00–$7FFF are protected in FLASH-2. The FLASH memory does not exist at some locations. The block protection range configuration is unaffected if FLASH memory does not exist in that range.
PAGE 65
FLASH-2 Mass Erase Operation 5.5 FLASH-2 Mass Erase Operation Use this step-by-step procedure to erase the entire FLASH-2 memory to read as logic 1: 1. Set both the ERASE bit and the MASS bit in the FLASH-2 Control Register (FL2CR). 2. Read the FLASH-2 Block Protect Register (FL2BPR). 3. Write to any FLASH-2 address within the FLASH-2 array with any data. NOTE If the address written to in Step 3 is within address space protected by the FLASH-2 Block Protect Register (FL2BPR), no erase will occur. 4. 5. 6.
PAGE 66
FLASH-2 Memory 5.6 FLASH-2 Page Erase Operation Use this step-by-step procedure to erase a page (128 bytes) of FLASH-2 memory to read as logic 1: 1. Set the ERASE bit and clear the MASS bit in the FLASH-2 Control Register (FL2CR). 2. Read the FLASH-2 Block Protect Register (FL2BPR). 3. Write any data to any FLASH-2 address within the address range of the page (128 byte block) to be erased. 4. Wait for time, tNVS. 5. Set the HVEN bit. 6. Wait for time, tERASE. 7. Clear the ERASE bit. 8.
PAGE 67
FLASH-2 Program Operation 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Wait for time, tNVS. Set the HVEN bit. Wait for time, tPGS. Write data byte to the FLASH-2 address to be programmed. Wait for time, t PROG. Repeat step 7 and 8 until all the bytes within the row are programmed. Clear the PGM bit. Wait for time, tNVH. Clear the HVEN bit. Wait for a time, tRCV, after which the memory can be accessed in normal read mode. The FLASH Programming Algorithm Flowchart is shown in Figure 5-4. NOTE A.
PAGE 68
FLASH-2 Memory 1 Algorithm for programming a row (64 bytes) of FLASH memory 2 3 4 5 6 7 8 Set PGM bit Read the FLASH block protect register Write any data to any FLASH address within the row address range desired Wait for a time, tnvs Set HVEN bit Wait for a time, tpgs Write data to the FLASH address to be programmed Wait for a time, tPROG Completed programming this row? Y N NOTE: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address pr
PAGE 69
Low-Power Modes 5.8 Low-Power Modes The WAIT and STOP instructions will place the MCU in low power consumption standby modes. 5.8.1 WAIT Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly; however, no memory activity will take place since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH.
PAGE 70
FLASH-2 Memory MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 71
Chapter 6 EEPROM-1 Memory 6.1 Introduction This chapter describes the 512 bytes of electrically erasable programmable read-only memory (EEPROM) residing at address range $0800 to $09FF. There are 1024 bytes of EEPROM available on the MC68HC908AS60A and MC68HC908AZ60A which are physically located in two 512 byte arrays. For information relating to the array covering address range $0600 to $07FF please see Chapter 7 EEPROM-2 Memory. 6.
PAGE 72
EEPROM-1 Memory Addr.
PAGE 73
Functional Description 6.4 Functional Description The 512 bytes of EEPROM-1 are located at $0800-$09FF and can be programmed or erased without an additional external high voltage supply. The program and erase operations are enabled through the use of an internal charge pump. For each byte of EEPROM, the write/erase endurance is 10,000 cycles. 6.4.
PAGE 74
EEPROM-1 Memory 6.4.3 EEPROM-1 Program/Erase Protection The EEPROM has a special feature that designates the 16 bytes of addresses from $08F0 to $08FF to be permanently secured. This program/erase protect option is enabled by programming the EEPRTCT bit in the EEPROM-1 Nonvolatile Register (EE1NVR) to a logic zero. Once the EEPRTCT bit is programmed to 0 for the first time: • Programming and erasing of secured locations $08F0 to $08FF is permanently disabled.
PAGE 75
Functional Description 6.4.5 EEPROM-1 Programming and Erasing The unprogrammed or erase state of an EEPROM bit is a logic 1. The factory default for all bytes within the EEPROM-1 array is $FF. The programming operation changes an EEPROM bit from logic 1 to logic 0 (programming cannot change a bit from logic 0 to a logic 1). In a single programming operation, the minimum EEPROM programming size is one bit; the maximum is eight bits (one byte).
PAGE 76
EEPROM-1 Memory 6.4.5.2 EEPROM-1 Programming The unprogrammed or erase state of an EEPROM bit is a logic 1. Programming changes the state to a logic 0. Only EEPROM bytes in the non-protected blocks and the EE1NVR register can be programmed. Use the following procedure to program a byte of EEPROM: 1. Clear EERAS1 and EERAS0 and set EELAT in the EE1CR.(A) NOTE If using the AUTO mode, also set the AUTO bit during Step 1. 2. 3. 4. 5. 6. 7. 8. Write the desired data to the desired EEPROM address.
PAGE 77
Functional Description 6.4.5.3 EEPROM-1 Erasing The programmed state of an EEPROM bit is logic 0. Erasing changes the state to a logic 1. Only EEPROM-1 bytes in the non-protected blocks and the EE1NVR register can be erased. Use the following procedure to erase a byte, block or the entire EEPROM-1 array: 1. Configure EERAS1 and EERAS0 for byte, block or bulk erase; set EELAT in EE1CR.(A) NOTE If using the AUTO mode, also set the AUTO bit in Step 1. 2. Byte erase: write any data to the desired address.
PAGE 78
EEPROM-1 Memory 6.5 EEPROM-1 Register Descriptions Four I/O registers and three nonvolatile registers control program, erase and options of the EEPROM-1 array. 6.5.1 EEPROM-1 Control Register This read/write register controls programming/erasing of the array. Address: $FE1D Bit 7 Read: Write: Reset: 6 0 UNUSED 0 5 4 3 2 1 Bit 0 EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM 0 0 0 0 0 0 0 = Unimplemented Figure 6-2.
PAGE 79
EEPROM-1 Register Descriptions AUTO — Automatic Termination of Program/Erase Cycle When AUTO is set, EEPGM is cleared automatically after the program/erase cycle is terminated by the internal timer. (See note D for 6.4.5.2 EEPROM-1 Programming, 6.4.5.3 EEPROM-1 Erasing, and 28.1.
PAGE 80
EEPROM-1 Memory EEBP[3:0] — EEPROM-1 Block Protection Bits These bits prevent blocks of EEPROM-1 array from being programmed or erased. 1 = EEPROM-1 array block is protected 0 = EEPROM-1 array block is unprotected Block Number (EEBPx) Address Range EEBP0 $0800–$087F EEBP1 $0880–$08FF EEBP2 $0900–$097F EEBP3 $0980–$09FF Table 6-4.
PAGE 81
EEPROM-1 Register Descriptions 6.5.3 EEPROM-1 Nonvolatile Register The contents of this register is loaded into the EEPROM-1 array configuration register (EE1ACR) after a reset. This register is erased and programmed in the same way as an EEPROM byte. (See 6.5.1 EEPROM-1 Control Register for individual bit descriptions). Address: Read: Write: $FE1C Bit 7 6 5 4 3 2 1 Bit 0 UNUSED UNUSED UNUSED EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 Reset: PV PV = Programmed value or 1 in the erased state.
PAGE 82
EEPROM-1 Memory EEDIVSECD — EEPROM-1 Divider Security Disable This bit enables/disables the security feature of the EE1DIV registers. When EE1DIV security feature is enabled, the state of the registers EE1DIVH and EE1DIVL are locked (including EEDIVSECD bit). The EE1DIVHNVR and EE1DIVLNVR nonvolatile memory registers are also protected from being erased/programmed.
PAGE 83
Low-Power Modes These two registers are protected from erase and program operations if the EEDIVSECD is set to logic 1 in the EE1DIVH (see EEPROM-1 Timebase Divider Register) or programmed to a logic 1 in the EE1DIVHNVR. NOTE Once EEDIVSECD in the EE1DIVHNVR is programmed to 0 and after a system reset, the EE1DIV security feature is permanently enabled because the EEDIVSECD bit in the EE1DIVH is always loaded with 0 thereafter.
PAGE 84
EEPROM-1 Memory MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 85
Chapter 7 EEPROM-2 Memory 7.1 Introduction This chapter describes the 512 bytes of electrically erasable programmable read-only memory (EEPROM) residing at address range $0600 to $07FF. There are 1024 bytes of EEPROM available on the MC68HC908AS60A and MC68HC908AZ60A which are physically located in two 512 byte arrays. For information relating to the array covering address range $0800 to $09FF please see Chapter 6 EEPROM-1 Memory. 7.
PAGE 86
EEPROM-2 Memory Addr.
PAGE 87
Functional Description 7.4 Functional Description The 512 bytes of EEPROM-2 are located at $0600-$07FF and can be programmed or erased without an additional external high voltage supply. The program and erase operations are enabled through the use of an internal charge pump. For each byte of EEPROM, the write/erase endurance is 10,000 cycles. 7.4.
PAGE 88
EEPROM-2 Memory 7.4.3 EEPROM-2 Program/Erase Protection The EEPROM has a special feature that designates the 16 bytes of addresses from $06F0 to $06FF to be permanently secured. This program/erase protect option is enabled by programming the EEPRTCT bit in the EEPROM-2 Nonvolatile Register (EE2NVR) to a logic zero. Once the EEPRTCT bit is programmed to 0 for the first time: • Programming and erasing of secured locations $06F0 to $06FF is permanently disabled.
PAGE 89
Functional Description 7.4.5 EEPROM-2 Programming and Erasing The unprogrammed or erase state of an EEPROM bit is a logic 1. The factory default for all bytes within the EEPROM-2 array is $FF. The programming operation changes an EEPROM bit from logic 1 to logic 0 (programming cannot change a bit from logic 0 to a logic 1). In a single programming operation, the minimum EEPROM programming size is one bit; the maximum is eight bits (one byte).
PAGE 90
EEPROM-2 Memory 7.4.5.2 EEPROM-2 Programming The unprogrammed or erase state of an EEPROM bit is a logic 1. Programming changes the state to a logic 0. Only EEPROM bytes in the non-protected blocks and the EE2NVR register can be programmed. Use the following procedure to program a byte of EEPROM: 1. Clear EERAS1 and EERAS0 and set EELAT in the EE2CR.(A) NOTE If using the AUTO mode, also set the AUTO bit during Step 1. 2. 3. 4. 5. 6. 7. 8. Write the desired data to the desired EEPROM address.
PAGE 91
Functional Description 7.4.5.3 EEPROM-2 Erasing The programmed state of an EEPROM bit is logic 0. Erasing changes the state to a logic 1. Only EEPROM-2 bytes in the non-protected blocks and the EE2NVR register can be erased. Use the following procedure to erase a byte, block or the entire EEPROM-2 array: 1. Configure EERAS1 and EERAS0 for byte, block or bulk erase; set EELAT in EE2CR.(A) NOTE If using the AUTO mode, also set the AUTO bit in Step 1. 2. Byte erase: write any data to the desired address.
PAGE 92
EEPROM-2 Memory 7.5 EEPROM-2 Register Descriptions Four I/O registers and three nonvolatile registers control program, erase and options of the EEPROM-2 array. 7.5.1 EEPROM-2 Control Register This read/write register controls programming/erasing of the array. Address: $FF7D Bit 7 Read: Write: Reset: 6 0 UNUSED 0 5 4 3 2 1 Bit 0 EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM 0 0 0 0 0 0 0 = Unimplemented Figure 7-2.
PAGE 93
EEPROM-2 Register Descriptions AUTO — Automatic Termination of Program/Erase Cycle When AUTO is set, EEPGM is cleared automatically after the program/erase cycle is terminated by the internal timer. (See note D for 7.4.5.2 EEPROM-2 Programming, 7.4.5.3 EEPROM-2 Erasing, and 28.1.
PAGE 94
EEPROM-2 Memory EEBP[3:0] — EEPROM-2 Block Protection Bits These bits prevent blocks of EEPROM-2 array from being programmed or erased. 1 = EEPROM-2 array block is protected 0 = EEPROM-2 array block is unprotected Block Number (EEBPx) Address Range EEBP0 $0600–$067F EEBP1 $0680–$06FF EEBP2 $0700–$077F EEBP3 $0780–$07FF Table 7-4.
PAGE 95
EEPROM-2 Register Descriptions 7.5.3 EEPROM-2 Nonvolatile Register The contents of this register is loaded into the EEPROM-2 array configuration register (EE2ACR) after a reset. This register is erased and programmed in the same way as an EEPROM byte. (See 7.5.1 EEPROM-2 Control Register for individual bit descriptions). Address: Read: Write: $FF7C Bit 7 6 5 4 3 2 1 Bit 0 UNUSED UNUSED UNUSED EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 Reset: PV PV = Programmed value or 1 in the erased state.
PAGE 96
EEPROM-2 Memory EEDIVSECD — EEPROM-2 Divider Security Disable This bit enables/disables the security feature of the EE2DIV registers. When EE2DIV security feature is enabled, the state of the registers EE2DIVH and EE2DIVL are locked (including EEDIVSECD bit). The EE2DIVHNVR and EE2DIVLNVR nonvolatile memory registers are also protected from being erased/programmed.
PAGE 97
Low-Power Modes These two registers are protected from erase and program operations if the EEDIVSECD is set to logic 1 in EE2DIVH or programmed to a logic 1 in EE2DIVHNVR. NOTE Once EEDIVSECD in the EE2DIVHNVR is programmed to 0 and after a system reset, the EE2DIV security feature is permanently enabled because the EEDIVSECD bit in the EE2DIVH is always loaded with 0 thereafter. Once this security feature is armed, erase and program mode are disabled for EE2DIVHNVR and EE2DIVLNVR.
PAGE 98
EEPROM-2 Memory MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 99
Chapter 8 Central Processor Unit (CPU) 8.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 8.
PAGE 100
Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 8-1. CPU Registers 8.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
PAGE 101
CPU Registers 8.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
PAGE 102
Central Processor Unit (CPU) 8.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 8-6.
PAGE 103
Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
PAGE 104
Central Processor Unit (CPU) 8.7 Instruction Set Summary Table 8-1 provides a summary of the M68HC08 instruction set.
PAGE 105
Instruction Set Summary Effect on CCR V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 (A) & (M) BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) Cycles Description Operand Operation Opcode Source Form Address Mode Table
PAGE 106
Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Clear Compare A with M Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X D
PAGE 107
Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine LDHX #opr LDHX opr Load H:X from M 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A ← (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 H:
PAGE 108
Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 8-1.
PAGE 109
Opcode Map SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte – – 1 – – – INH 83 9 CCR ← (A) INH 84 2 X ← (A) – – – – – – INH 97 1 A ← (CCR) – – – – – – INH 85 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH
PAGE 110
MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
PAGE 111
Chapter 9 System Integration Module (SIM) 9.1 Introduction This chapter describes the system integration module (SIM), which supports up to 32 external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 9-1. Figure 9-2 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing.
PAGE 112
System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO CGM) SIM COUNTER COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) ÷2 CLOCK CONTROL RESET PIN LOGIC INTERNAL CLOCKS CLOCK GENERATORS LVI (FROM LVI MODULE) POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) SIM RESET STATUS REGISTER RESET INTERRUPT SOURCES INTERRUPT CONTROL AND PR
PAGE 113
SIM Bus Clock Control and Generation Table 9-2 shows the internal signal names used in this chapter. Table 9-2.
PAGE 114
System Integration Module (SIM) 9.2.2 Clock Startup from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after 4096 CGMXCLK cycles. The RST pin is driven low by the SIM during this entire period. The bus clocks start upon completion of the timeout. 9.2.
PAGE 115
Reset and System Initialization 9.3.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 9-5). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR (see Figure 9-6).
PAGE 116
System Integration Module (SIM) 9.3.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. Another sixty-four CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: • A POR pulse is generated.
PAGE 117
SIM Counter 9.3.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources.
PAGE 118
System Integration Module (SIM) 9.4.3 SIM Counter and Reset States External reset has no effect on the SIM counter. See 9.6.2 Stop Mode for details. The SIM counter is free-running after all reset states. See 9.3.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences. 9.
PAGE 119
Program Exception Control FROM RESET YES BREAK INTERRUPT? I BIT SET? NO YES I BIT SET? NO IRQ1 INTERRUPT? YES NO STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. (AS MANY INTERRUPTS AS EXIST ON CHIP) FETCH NEXT INSTRUCTION. SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS. NO EXECUTE INSTRUCTION. Figure 9-9. Interrupt Processing MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 120
System Integration Module (SIM) MODULE INTERRUPT I BIT IAB SP – 4 IDB SP – 3 CCR SP – 2 A SP – 1 X SP PC – 1 [7:0] PC PC–1[15:8] PC + 1 OPCODE OPERAND R/W Figure 9-10. Interrupt Recovery 9.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts.
PAGE 121
Low-Power Modes The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M68HC05, M6805 and M146805 Families the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. 9.5.1.
PAGE 122
System Integration Module (SIM) 9.6.1 Wait Mode In wait mode, the CPU clocks are inactive while one set of peripheral clocks continue to run. Figure 9-12 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
PAGE 123
Low-Power Modes 9.6.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset also causes an exit from stop mode. The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping the CPU and peripherals.
PAGE 124
System Integration Module (SIM) 9.7 SIM Registers The SIM has three memory mapped registers. 9.7.1 SIM Break Status Register The SIM break status register contains a flag to indicate that a break caused an exit from wait mode. Address: Read: Write: $FE00 Bit 7 6 5 4 3 2 R R R R R R R = Reserved 1 Bit 0 BW R See Note Reset: 0 NOTE: Writing a logic 0 clears BW Figure 9-17.
PAGE 125
SIM Registers ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset was caused by the LVI circuit 0 = POR or read of SRSR 9.7.
PAGE 126
System Integration Module (SIM) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 127
Chapter 10 Clock Generator Module (CGM) 10.1 Introduction The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, from which the system clocks are derived. CGMOUT is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency generator designed for use with 1-MHz to 8-MHz crystals or ceramic resonators.
PAGE 128
Clock Generator Module (CGM) CGMXCLK OSC1 CLOCK SELECT CIRCUIT CGMRDV ÷2 CGMRCLK A CGMOUT B S* *When S = 1, CGMOUT = B BCS PTC3 VDDA CGMXFC VSS MONITOR MODE VRS7–VRS4 USER MODE PHASE DETECTOR VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER PLL ANALOG LOCK DETECTOR LOCK BANDWIDTH CONTROL AUTO ACQ INTERRUPT CONTROL PLLIE CGMINT PLLF MUL7–MUL4 CGMVDV FREQUENCY DIVIDER CGMVCLK Figure 10-1. CGM Block Diagram MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 129
Functional Description Register Name Bit 7 Read: 6 5 4 PLLON BCS 1 0 ACQ XLD PLLF PLLIE 3 2 1 Bit 0 1 1 1 1 1 1 1 1 0 0 0 0 PLL Control Register (PCTL) Write: Reset: Read: PLL Bandwidth Control Register (PBWrite: WC) Reset: 0 0 LOCK AUTO 0 0 0 0 0 0 0 0 MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 0 1 1 0 0 1 1 0 Read: PLL Programming Register (PPG) Write: Reset: = Unimplemented Figure 10-2. I/O Register Summary Table 10-1.
PAGE 130
Clock Generator Module (CGM) 10.3.2.1 Circuits The PLL consists of these circuits: • Voltage-controlled oscillator (VCO) • Modulo VCO frequency divider • Phase detector • Loop filter • Lock detector The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fCGMVRS.
PAGE 131
Functional Description 10.3.2.3 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See 10.5.2 PLL Bandwidth Control Register.
PAGE 132
Clock Generator Module (CGM) 10.3.2.4 Programming the PLL Use this 9-step procedure to program the PLL. Table 10-2 lists the variables used and their meaning (Please also reference Figure 10-1). Table 10-2.
PAGE 133
Functional Description 7. Using the value 4.9152 MHz for fNOM, calculate the VCO linear range multiplier, L. The linear range multiplier controls the frequency range of the PLL. f CGMVCLK L = round ⎛⎝ ------------------------⎞⎠ f NOM 32 MHz 4.9152 MHz Example: L = -------------------------------- = 7 8. Calculate the VCO center-of-range frequency, fCGMVRS. The center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL.
PAGE 134
Clock Generator Module (CGM) factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock. 10.3.4 CGM External Connections In its typical configuration, the CGM requires seven external components. Five of these are for the crystal oscillator and two are for the PLL.
PAGE 135
I/O Signals 10.4 I/O Signals The following paragraphs describe the CGM input/output (I/O) signals. 10.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 10.4.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. 10.4.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is connected to this pin.
PAGE 136
Clock Generator Module (CGM) 10.5 CGM Registers Three registers control and monitor operation of the CGM: • PLL control register (PCTL) • PLL bandwidth control register (PBWC) • PLL programming register (PPG) 10.5.1 PLL Control Register The PLL control register contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit.
PAGE 137
CGM Registers it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. See 10.3.3 Base Clock Selector Circuit. Reset and the STOP instruction clear the BCS bit.
PAGE 138
Clock Generator Module (CGM) In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode XLD — Crystal Loss Detect Bit When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit can indicate whether the crystal reference frequency is active or not.
PAGE 139
Interrupts Table 10-3. VCO Frequency Multiplier (N) Selection MUL7:MUL6:MUL5:MUL4 VCO Frequency Multiplier (N) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15 NOTE The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1). VRS7–VRS4 — VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L, which controls the hardware center-of-range frequency, fVRS. (See 10.3.2.1 Circuits, 10.3.
PAGE 140
Clock Generator Module (CGM) NOTE Software can select the CGMVCLK divided by two as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit. 10.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 10.7.1 Wait Mode The CGM remains active in wait mode.
PAGE 141
Acquisition/Lock Time Specifications 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz ±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100 kHz noise hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5% of the 100-kHz step input.
PAGE 142
Clock Generator Module (CGM) Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause drastic changes in the operation of the PLL.
PAGE 143
Acquisition/Lock Time Specifications In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (See 10.3.2.3 Manual and Automatic PLL Bandwidth Modes). A certain number of clock cycles, nACQ, is required to ascertain that the PLL is within the tracking mode entry tolerance, ΔTRK, before exiting acquisition mode. A certain number of clock cycles, nTRK, is required to ascertain that the PLL is within the lock mode entry tolerance, ΔLock.
PAGE 144
Clock Generator Module (CGM) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 145
Chapter 11 Configuration Register (CONFIG-1) 11.1 Introduction This chapter describes the configuration register (CONFIG-1), which contains bits that configure these options: • Resets caused by the LVI module • Power to the LVI module • LVI enabled during stop mode • Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) • Computer operating properly module (COP) • Stop instruction enable/disable. 11.2 Functional Description The configuration register is a write-once register.
PAGE 146
Configuration Register (CONFIG-1) LVIRST — LVI Reset Enable Bit LVIRST enables the reset signal from the LVI module. (See Chapter 16 Low-Voltage Inhibit (LVI)). 1 = LVI module resets enabled 0 = LVI module resets disabled LVIPWR — LVI Power Enable Bit LVIPWR enables the LVI module. (See Chapter 16 Low-Voltage Inhibit (LVI)).
PAGE 147
Chapter 12 Configuration Register (CONFIG-2) 12.1 Introduction This chapter describes the configuration register (CONFIG-2). This register contains bits that configure these options: • Configures the device to either the MC68HC08AZxx emulator or the MC68HC08ASxx emulator • Disables the CAN module 12.2 Functional Description The configuration register is a write-once register. Out of reset, the configuration register will read the default.
PAGE 148
Configuration Register (CONFIG-2) AZxx — AZxx Emulator Enable Bit AZxx enables the MC68HC08AZxx emulator configuration. This bit will be 0 out of reset. 1 = MC68HC08AZxx emulator enabled 0 = MC68HC08ASxx emulator enabled NOTE AZxx bit is reset by a POWER-ON-RESET only. MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 149
Chapter 13 Break Module (BRK) 13.1 Introduction The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 13.2 Features • • • • Accessible I/O Registers during Break Interrupts CPU-Generated Break Interrupts Software-Generated Break Interrupts COP Disabling during Break Interrupts 13.
PAGE 150
Break Module (BRK) IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] CONTROL BREAK 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] Figure 13-1.
PAGE 151
Low-Power Modes 13.3.1 Flag Protection During Break Interrupts The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. 13.3.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress.
PAGE 152
Break Module (BRK) 13.5.1 Break Status and Control Register The break status and control register contains break module enable and status bits. Address: Read: Write: Reset: $FE0E Bit 7 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 13-3. Break Status and Control Register (BSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit 7. Reset clears the BRKE bit.
PAGE 153
Chapter 14 Monitor ROM (MON) 14.1 Introduction This chapter describes the monitor ROM (MON). The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. 14.2 Features Features of the monitor ROM include: • Normal User-Mode Pin Functionality • One Pin Dedicated to Serial Communication between Monitor ROM and Host Computer • Standard Mark/Space Non-Return-to-Zero (NRZ) Communication with Host Computer • Up to 28.
PAGE 154
Monitor ROM (MON) VDD 68HC08 10 kΩ RST 0.1 μF VHI 1 KΩ IRQ 9.1V CGMXFC 1 10 μF + 3 4 10 μF MC145407 0.022 μF 20 + 2 OSC1 20 pF 17 + + 10 μF 18 10 μF * X1 4.9152 MHz 10 MΩ OSC2 VDD VDDA 20 pF 19 VDDA/VDDAREF 0.1 μF VSSA VSS DB-25 2 5 16 3 6 15 0.1 μF VDD VDD 7 VDD 1 MC74HC125 2 3 6 5 4 7 NOTE: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4 Position B — Bus clock = CGMXCLK ÷ 2 VDD 14 10 kΩ PTA0 PTC3 VDD VDD 10 kΩ A (SEE NOTE.
PAGE 155
Functional Description 14.3.1 Entering Monitor Mode Table 14-1 shows the pin conditions for entering monitor mode. IRQ Pin PTC0 Pin PTC1 Pin PTA0 Pin PTC3 Pin Table 14-1. Mode Selection Mode VHI(1) 1 0 1 1 Monitor CGMXCLK CGMVCLK ----------------------------- or ----------------------------2 2 CGMOUT -------------------------2 VHI(1) 1 0 1 0 Monitor CGMXCLK CGMOUT -------------------------2 CGMOUT Bus Frequency 1. For VHI, 28.1.4 5.0 Volt DC Electrical Characteristics, and 28.1.
PAGE 156
Monitor ROM (MON) 14.3.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 14-2 and Figure 14-3.) The data transmit and receive rate can be anywhere up to 28.8 kBaud. Transmit and receive baud rates must be identical. START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 STOP BIT BIT 7 NEXT START BIT Figure 14-2.
PAGE 157
Functional Description 14.3.5 Commands The monitor ROM uses these commands: • READ, read memory • WRITE, write memory • IREAD, indexed read • IWRITE, indexed write • READSP, read stack pointer • RUN, run user program A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 14-3.
PAGE 158
Monitor ROM (MON) Table 14-5. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command Sequence SENT TO MONITOR IREAD IREAD DATA DATA RESULT ECHO Table 14-6.
PAGE 159
Functional Description Table 14-8. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode $28 Command Sequence SENT TO MONITOR RUN RUN ECHO 14.3.6 MC68HC908AS60A Baud Rate With a 4.9152-MHz crystal and the PTC3 pin at logic 1 during reset, data is transferred between the monitor and host at 4800 baud. If the PTC3 pin is at logic 0 during reset, the monitor baud rate is 9600.
PAGE 160
Monitor ROM (MON) 14.3.7 MC68HC908AZ60A Baud Rate The MC68HC908AZ60A features a monitor mode which is optimised to operate with either a 4.9152 MHz crystal clock source (or multiples of 4.9152 MHz) or a 4 MHz crystal (or multiples of 4 MHz). This supports designs which use the MSCAN module, which is generally clocked from a 4 MHz, 8 MHz or 16 MHZ internal reference clock. The table below outlines the available baud rates for a range of crystals and how they can match to a PC baud rate.
PAGE 161
Functional Description VDD 4096 + 32 CGMXCLK CYCLES RST Command Byte 8 Byte 2 Byte 1 24 BUS CYCLES (MINIMUM) FROM HOST PA0 4 Break 2 1 Command Echo NOTE: 1 = Echo delay (2 bit times) 2 = Data return delay (2 bit times) 4 = Wait 1 bit time before sending next byte. 1 Byte 8 Echo Byte 1 Echo FROM MCU 1 Byte 2 Echo 4 1 Figure 14-6.
PAGE 162
Monitor ROM (MON) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 163
Chapter 15 Computer Operating Properly (COP) 15.1 Introduction The COP module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by periodically clearing the COP counter. 15.2 Functional Description The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler.
PAGE 164
Computer Operating Properly (COP) 12-BIT COP PRESCALER CLEAR STAGES 4–12 STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH CLEAR ALL STAGES CGMXCLK COPCTL WRITE RESET RESET STATUS REGISTER 6-BIT COP COUNTER COPD FROM CONFIG-1 RESET COPCTL WRITE CLEAR COP COUNTER COPL FROM CONFIG-1 Figure 15-1. COP Block Diagram 15.3.1 CGMXCLK CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency. 15.3.
PAGE 165
COP Control Register 15.3.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 15.3.7 COPD The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. (See Chapter 11 Configuration Register (CONFIG-1)). 15.3.8 COPL The COPL signal reflects the state of the COP rate select bit. (COPL) in the configuration register. (See Chapter 11 Configuration Register (CONFIG-1)). 15.
PAGE 166
Computer Operating Properly (COP) 15.7.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. 15.
PAGE 167
Chapter 16 Low-Voltage Inhibit (LVI) 16.1 Introduction This chapter describes the low-voltage inhibit module (LVI47, Version A), which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls to the LVI trip voltage. 16.
PAGE 168
Low-Voltage Inhibit (LVI) VDD LVIPWR FROM CONFIG-1 FROM CONFIG-1 CPU CLOCK LOW VDD DETECTOR LVIRST VDD DIGITAL FILTER VDD > LVITRIP = 0 LVI RESET VDD < LVITRIP = 1 Stop Mode Filter Bypass ANLGTRIP LVIOUT LVISTOP FROM CONFIG-1 Figure 16-1. LVI Module Block Diagram Addr. Register Name Bit 7 Read: LVIOUT $FE0F 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 LVI Status Register (LVISR) Write: = Unimplemented Figure 16-2. LVI I/O Register Summary 16.3.
PAGE 169
LVI Status Register 16.4 LVI Status Register The LVI status register flags VDD voltages below the LVITRIPF level. Address: $FE0F Bit 7 6 5 4 3 2 1 Bit 0 Read: LVIOUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 16-3. LVI Status Register (LVISR) LVIOUT — LVI Output Bit This read-only flag becomes set when the VDD voltage falls below the LVITRIPF voltage for 32 to 40 CGMXCLK cycles. (See Table 16-1). Reset clears the LVIOUT bit. Table 16-1.
PAGE 170
Low-Voltage Inhibit (LVI) 16.6.2 Stop Mode With the LVISTOP and LVIPWR bits in the configuration register programmed to a logic 1, the LVI module will be active after a STOP instruction. Because CPU clocks are disabled during stop mode, the LVI trip must bypass the digital filter to generate a reset and bring the MCU out of stop. With the LVIPWR bit in the configuration register programmed to logic 1 and the LVISTOP bit at a logic 0, the LVI module will be inactive after a STOP instruction.
PAGE 171
Chapter 17 External Interrupt Module (IRQ) 17.1 Introduction This chapter describes the nonmaskable external interrupt (IRQ) input. 17.2 Features Features include: • Dedicated External Interrupt Pin (IRQ) • Hysteresis Buffer • Programmable Edge-Only or Edge- and Level-Interrupt Sensitivity • Automatic Interrupt Acknowledge 17.3 Functional Description A falling edge applied to the external interrupt pin can latch a CPU interrupt request. Figure 17-1 shows the structure of the IRQ module.
PAGE 172
External Interrupt Module (IRQ) INTERNAL ADDRESS BUS ACK TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER VDD IRQF D CLR Q SYNCHRONIZER CK IRQ IRQ INTERRUPT REQUEST IRQ LATCH IMASK MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC Figure 17-1. IRQ Block Diagram Addr. $001A Register Name Bit 7 6 5 4 3 2 Read: 0 0 0 0 IRQF 0 Write: R R R R R ACK IRQ Status/Control Register (ISCR) R 1 Bit 0 IMASK MODE = Reserved Figure 17-2.
PAGE 173
Functional Description FROM RESET YES I BIT SET? NO INTERRUPT? YES NO STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS. NO EXECUTE INSTRUCTION. Figure 17-3. IRQ Interrupt Flowchart MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 174
External Interrupt Module (IRQ) 17.4 IRQ Pin A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge sensitive and low-level sensitive. With MODE set, both of the following actions must occur to clear the IRQ latch: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch.
PAGE 175
IRQ Status and Control Register 17.6 IRQ Status and Control Register The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module.
PAGE 176
External Interrupt Module (IRQ) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 177
Chapter 18 Serial Communications Interface (SCI) 18.1 Introduction The SCI allows asynchronous communications with peripheral devices and other MCUs. 18.
PAGE 178
Serial Communications Interface (SCI) Table 18-1. Pin Name Conventions Generic Pin Names RxD TxD Full Pin Names PTE1/SCRxD PTE0/SCTxD 18.4 Functional Description Figure 18-1 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator.
PAGE 179
Functional Description Register Name Bit 7 6 5 4 3 2 1 Bit 0 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK Reset: 0 0 0 0 0 0 0 0 Read: R8 T8 R R ORIE NEIE FEIE PEIE Read: SCI Control Register 1 (SCC1) Write: Reset: Read: SCI Control Register 2 (SCC2) Write: SCI Control Register 3 (SCC3) Write: Reset: U U 0 0 0 0 0 0 Read: SCTE TC SCRF IDLE OR NF FE PE Reset: 1 1 0 0 0 0 0 0 Read: 0 0
PAGE 180
Serial Communications Interface (SCI) 18.4.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 18-3. 8-BIT DATA FORMAT (BIT M IN SCC1 CLEAR) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 PARITY OR DATA BIT BIT 6 9-BIT DATA FORMAT (BIT M IN SCC1 SET) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT PARITY OR DATA BIT BIT 7 BIT 8 STOP BIT NEXT START BIT Figure 18-3. SCI Data Formats 18.4.
PAGE 181
Functional Description INTERNAL BUS ÷ 16 SCI DATA REGISTER SCP1 11-BIT TRANSMIT SHIFT REGISTER STOP CGMXCLK BAUD DIVIDER SCP0 SCR1 H SCR2 8 7 6 5 4 3 START PRESCALER ÷4 2 1 0 L TxD MSB TXINV T8 BREAK (ALL ZEROS) PARITY GENERATION PTY PREAMBLE (ALL ONES) PEN SHIFT ENABLE M LOAD FROM SCDR TRANSMITTER CPU INTERRUPT REQUEST SCR0 TRANSMITTER CONTROL LOGIC SCTE SCTE SCTIE SBK LOOPS SCTIE ENSCI TC TE TC TCIE TCIE Figure 18-4.
PAGE 182
Serial Communications Interface (SCI) Register Name Bit 7 6 5 4 3 2 1 Bit 0 SCTE TC SCRF IDLE OR NF FE PE Reset: 1 1 0 0 0 0 0 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 SCI Data Register (SCDR) Write: T7 T6 T5 T4 T3 T2 T1 T0 Read: SCI Status Register 1 (SCS1) Write: Reset: Read: Unaffected by Reset 0 0 SCP1 SCP0 R SCR2 SCR1 SCR0 0 0 0 0 0 0 SCI Baud Rate Register (SCBR) Write: Reset: 0 0 = Unimplemented U = Unaffected R = Reserved Figure 18-5.
PAGE 183
Functional Description 18.4.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress.
PAGE 184
Serial Communications Interface (SCI) INTERNAL BUS SCR1 SCP0 SCR0 BAUD DIVIDER ÷ 16 CGMXCLK DATA RECOVERY RxD BKF ALL ZEROS CPU INTERRUPT REQUEST ERROR CPU INTERRUPT REQUEST RPF M WAKE ILTY PEN PTY STOP PRESCALER H ALL ONES ÷4 SCI DATA REGISTER START SCR2 11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 0 RWU SCRF WAKEUP LOGIC IDLE R8 PARITY CHECKING IDLE ILIE SCRF SCRIE L MSB SCP1 ILIE SCRIE OR ORIE NF NEIE FE FEIE PE PEIE OR ORIE NF NEIE FE FEIE PE PEIE Figure 18-6.
PAGE 185
Functional Description Register Name Bit 7 6 5 4 3 2 1 Bit 0 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK Reset: 0 0 0 0 0 0 0 0 Read: R8 T8 R R ORIE NEIE FEIE PEIE Read: SCI Control Register 1 (SCC1) Write: Reset: Read: SCI Control Register 2 (SCC2) Write: SCI Control Register 3 (SCC3) Write: Reset: U U 0 0 0 0 0 0 Read: SCTE TC SCRF IDLE OR NF FE PE Reset: 1 1 0 0 0 0 0 0 Read: 0 0
PAGE 186
Serial Communications Interface (SCI) 18.4.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 18.4.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin.
PAGE 187
Functional Description To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 18-5 summarizes the results of the start bit verification samples. Table 18-5. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
PAGE 188
Serial Communications Interface (SCI) To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 18-7 summarizes the results of the stop bit samples. Table 18-7. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 18.4.3.
PAGE 189
Functional Description For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 18-9, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is 154 – 147 × 100 = 4.
PAGE 190
Serial Communications Interface (SCI) The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 170 – 176 × 100 = 3.53%. -------------------------170 18.4.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state.
PAGE 191
Low-Power Modes • • • Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests. Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests.
PAGE 192
Serial Communications Interface (SCI) 18.7 I/O Signals Port E shares two of its pins with the SCI module. The two SCI I/O pins are: • PTE0/SCTxD — Transmit data • PTE1/SCRxD — Receive data 18.7.1 PTE0/SCTxD (Transmit Data) The PTE0/SCTxD pin is the serial data output from the SCI transmitter. The SCI shares the PTE0/SCTxD pin with port E. When the SCI is enabled, the PTE0/SCTxD pin is an output regardless of the state of the DDRE2 bit in data direction register E (DDRE). 18.7.
PAGE 193
I/O Registers Address: Read: Write: Reset: $0013 Bit 7 6 5 4 3 2 1 Bit 0 LOOPS ENSCI TXINV M WAKE ILLTY PEN PTY 0 0 0 0 0 0 0 0 Figure 18-11. SCI Control Register 1 (SCC1) LOOPS — Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit.
PAGE 194
Serial Communications Interface (SCI) 0 = Idle character bit count begins after start bit PEN — Parity Enable Bit This read/write bit enables the SCI parity function. (See Table 18-8). When enabled, the parity function inserts a parity bit in the most significant bit position. (See Table 18-7). Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled PTY — Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity.
PAGE 195
I/O Registers Address: Read: Write: Reset: $0014 Bit 7 6 5 4 3 2 1 Bit 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 18-12. SCI Control Register 2 (SCC2) SCTIE — SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Setting the SCTIE bit in SCC3 enables the SCTE bit to generate CPU interrupt requests. Reset clears the SCTIE bit.
PAGE 196
Serial Communications Interface (SCI) RE — Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1.
PAGE 197
I/O Registers R8 — Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits. When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 — Transmitted Bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character.
PAGE 198
Serial Communications Interface (SCI) Address: Read: $0016 Bit 7 6 5 4 3 2 1 Bit 0 SCTE TC SCRF IDLE OR NF FE PE 1 0 0 0 0 0 0 Write: Reset: 1 = Unimplemented Figure 18-14. SCI Status Register 1 (SCS1) SCTE — SCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an SCI transmitter CPU interrupt request.
PAGE 199
I/O Registers OR — Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit.
PAGE 200
Serial Communications Interface (SCI) FE — Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected PE — Receiver Parity Error Bit This clearable, read-only bit is set when the SCI detects a parity error in incoming data.
PAGE 201
I/O Registers 18.8.6 SCI Data Register The SCI data register is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register. Address: $0018 Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by Reset Figure 18-17.
PAGE 202
Serial Communications Interface (SCI) Table 18-10. SCI Baud Rate Selection SCR[2:1:0] Baud Rate Divisor (BD) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Use the following formula to calculate the SCI baud rate: f Crystal Baud rate = -----------------------------------64 × PD × BD where: fCrystal = crystal frequency PD = prescaler divisor BD = baud rate divisor Table 18-11 shows the SCI baud rates that can be generated with a 4.9152-MHz crystal.
PAGE 203
I/O Registers Table 18-11. SCI Baud Rate Selection Examples SCP[1:0] Prescaler Divisor (PD) SCR[2:1:0] Baud Rate Divisor (BD) Baud Rate (fCrystal = 4.
PAGE 204
Serial Communications Interface (SCI) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 205
Chapter 19 Serial Peripheral Interface (SPI) 19.1 Introduction This chapter describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 19.
PAGE 206
Serial Peripheral Interface (SPI) The generic names of the SPI I/O registers are: • SPI control register (SPCR) • SPI status and control register (SPSCR) • SPI data register (SPDR) Table 19-2 shows the names and the addresses of the SPI I/O registers. Table 19-2. I/O Register Addresses Register Name Address SPI Control Register (SPCR) $0010 SPI Status and Control Register (SPSCR) $0011 SPI Data Register (SPDR) $0012 19.
PAGE 207
Functional Description INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER BUS CLOCK 7 6 5 4 3 2 1 MISO 0 ÷2 CLOCK DIVIDER MOSI ÷8 RECEIVE DATA REGISTER ÷ 32 PIN CONTROL LOGIC ÷ 128 SPMSTR SPE CLOCK SELECT SPR1 SPSCK M CLOCK LOGIC S SS SPR0 SPMSTR TRANSMITTER CPU INTERRUPT REQUEST CPHA MODFEN CPOL SPWOM ERRIE SPI CONTROL SPTIE RECEIVER/ERROR CPU INTERRUPT REQUEST SPRIE SPE SPRF SPTE OVRF MODF Figure 19-2.
PAGE 208
Serial Peripheral Interface (SPI) 19.4.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR (SPCR $0010), is set. NOTE Configure the SPI modules as master and slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. See 19.13.1 SPI Control Register. Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI module by writing to the SPI data register.
PAGE 209
Transmission Formats The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed, which is twice as fast as the fastest master SPSCK clock that can be generated. The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master.
PAGE 210
Serial Peripheral Interface (SPI) 19.5.2 Transmission Format When CPHA = 0 Figure 19-4 shows an SPI transmission in which CPHA (SPCR) is logic 0. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SCK: one for CPOL = 0 and another for CPOL = 1.
PAGE 211
Transmission Formats 19.5.3 Transmission Format When CPHA = 1 Figure 19-5 shows an SPI transmission in which CPHA (SPCR) is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SCK: one for CPOL = 0 and another for CPOL = 1.
PAGE 212
Serial Peripheral Interface (SPI) delay will be no longer than a single SPI bit time. That is, the maximum delay between the write to SPDR and the start of the SPI transmission is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
PAGE 213
Error Conditions 19.6 Error Conditions Two flags signal SPI error conditions: 1. Overflow (OVRF in SPSCR) — Failing to read the SPI data register before the next byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read by accessing the SPI data register. OVRF is in the SPI status and control register. 2.
PAGE 214
Serial Peripheral Interface (SPI) The first part of Figure 19-7 shows how to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by the second transmission example, the OVRF flag can be set in between the time that SPSCR and SPDR are read. In this case, an overflow can be easily missed. Since no more SPRF interrupts can be generated until this OVRF is serviced, it will not be obvious that bytes are being lost as more transmissions are completed.
PAGE 215
Error Conditions In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes low. A mode fault in a master SPI causes the following events to occur: • If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request. • The SPE bit is cleared. • The SPTE bit is set. • The SPI state counter is cleared. • The data direction register of the shared I/O port regains control of port drivers.
PAGE 216
Serial Peripheral Interface (SPI) 19.7 Interrupts Four SPI status flags can be enabled to generate CPU interrupt requests: Table 19-3.
PAGE 217
Queuing Transmission Data 19.8 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates when the transmit data buffer is ready to accept new data. Write to the SPI data register only when the SPTE bit is high.
PAGE 218
Serial Peripheral Interface (SPI) 19.9 Resetting the SPI Any system reset completely resets the SPI. Partial reset occurs whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the following occurs: • The SPTE flag is set. • Any transmission currently in progress is aborted. • The shift register is cleared. • The SPI state counter is cleared, making it ready for a new complete transmission. • All the SPI port logic is defaulted back to being general-purpose I/O.
PAGE 219
I/O Signals To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit.
PAGE 220
Serial Peripheral Interface (SPI) When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port. 19.12.4 SS (Slave Select) The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission. 19.
PAGE 221
I/O Registers 19.12.5 VSS (Clock Ground) VSS is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. To reduce the ground return path loop and minimize radio frequency (RF) emissions, connect the ground pin of the slave to the VSS pin. 19.13 I/O Registers Three registers control and monitor SPI operation: • SPI control register (SPCR $0010) • SPI status and control register (SPSCR $0011) • SPI data register (SPDR $0012) 19.13.
PAGE 222
Serial Peripheral Interface (SPI) CPHA — Clock Phase Bit This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure 19-4 and Figure 19-5.) To transmit data between SPI modules, the SPI modules must have identical CPHA bits. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between bytes. (See Figure 19-11). Reset sets the CPHA bit. When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission.
PAGE 223
I/O Registers Address: $0011 Bit 7 Read: SPRF Write: Reset: 6 ERRIE 0 0 R = Reserved 5 4 3 OVRF MODF SPTE 0 0 1 2 1 Bit 0 MODFEN SPR1 SPR0 0 0 0 = Unimplemented Figure 19-13. SPI Status and Control Register (SPSCR) SPRF — SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.
PAGE 224
Serial Peripheral Interface (SPI) For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE will be set again within two bus cycles since the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible.
PAGE 225
I/O Registers 19.13.3 SPI Data Register The SPI data register is the read/write buffer for the receive data register and the transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate buffers that can contain different values. (See Figure 19-2.
PAGE 226
Serial Peripheral Interface (SPI) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 227
Chapter 20 Timer Interface Module B (TIMB) 20.1 Introduction This chapter describes the timer interface module (TIMB). The TIMB is a 2-channel timer that provides a timing reference with input capture, output compare and pulse width modulation functions. Figure 20-1 is a block diagram of the TIMB. The TIMB module is feature of the MC68HC908AZ60A only. For further information regarding timers on M68HC08 family devices, please consult the HC08 Timer Reference Manual, TIM08RM/AD. 20.
PAGE 228
Timer Interface Module B (TIMB) TCLK PTD4/ATD12/TBCLK PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER INTERRUPT LOGIC TOF TOIE 16-BIT COMPARATOR TMODH:TMODL ELS0B CHANNEL 0 ELS0A TOV0 CH0MAX 16-BIT COMPARATOR TCH0H:TCH0L PTF4 LOGIC CH0F INTERRUPT LOGIC 16-BIT LATCH MS0A ELS1B CHANNEL 1 CH0IE MS0B ELS1A TOV1 CH1MAX 16-BIT COMPARATOR TCH1H:TCH1L PTF5 LOGIC CH1F PTF5/TBCH1 INTERRUPT LOGIC 16-BIT LATCH CH1IE MS1A PTF4/TBCH0 Figure 20-1.
PAGE 229
Functional Description 20.3 Functional Description Figure 20-1 shows the TIMB structure. The central component of the TIMB is the 16-bit TIMB counter that can operate as a free-running counter or a modulo up-counter. The TIMB counter provides the timing reference for the input capture and output compare functions. The TIMB counter modulo registers, TBMODH–TBMODL, control the modulo value of the TIMB counter. Software can read the TIMB counter value at any time without affecting the counting sequence.
PAGE 230
Timer Interface Module B (TIMB) 20.3.3 Output Compare With the output compare function, the TIMB can generate a periodic pulse with a programmable polarity, duration and frequency. When the counter reaches the value in the registers of an output compare channel, the TIMB can set, clear or toggle the channel pin. Output compares can generate TIMB CPU interrupt requests. 20.3.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 20.3.
PAGE 231
Functional Description 20.3.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIMB can generate a PWM signal. The value in the TIMB counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIMB counter modulo registers. The time between overflows is the period of the PWM signal.
PAGE 232
Timer Interface Module B (TIMB) Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value.
PAGE 233
Functional Description 20.3.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIMB status and control register (TBSC): a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP. b. Reset the TIMB counter and prescaler by setting the TIMB reset bit, TRST. 2. In the TIMB counter modulo registers (TBMODH–TBMODL) write the value for the required PWM period. 3.
PAGE 234
Timer Interface Module B (TIMB) 20.4 Interrupts The following TIMB sources can generate interrupt requests: • TIMB overflow flag (TOF) — The TOF bit is set when the TIMB counter value reaches the modulo value programmed in the TIMB counter modulo registers. The TIMB overflow interrupt enable bit, TOIE, enables TIMB overflow CPU interrupt requests. TOF and TOIE are in the TIMB status and control register.
PAGE 235
I/O Signals 20.7 I/O Signals Port D shares one of its pins with the TIMB. Port F shares two of its pins with the TIMB. PTD4/ATD12/TBCLK is an external clock input to the TIMB prescaler. The two TIMB channel I/O pins are PTF4/TBCH0 and PTF5/TBCH1. 20.7.1 TIMB Clock Pin (PTD4/ATD12/TBCLK) PTD4/ATD12/TBCLK is an external clock input that can be the clock source for the TIMB counter instead of the prescaled internal bus clock.
PAGE 236
Timer Interface Module B (TIMB) Address: $0040 Bit 7 6 5 TOIE TSTOP 1 Read: TOF Write: 0 Reset: 0 0 R = Reserved 4 3 0 0 TRST R 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 Figure 20-4. TIMB Status and Control Register (TBSC) TOF — TIMB Overflow Flag Bit This read/write flag is set when the TIMB counter reaches the modulo value programmed in the TIMB counter modulo registers. Clear TOF by reading the TIMB status and control register when TOF is set and then writing a logic 0 to TOF.
PAGE 237
I/O Registers PS[2:0] — Prescaler Select Bits These read/write bits select either the PTD4/ATD12/TBCLK pin or one of the seven prescaler outputs as the input to the TIMB counter as Table 20-1 shows. Reset clears the PS[2:0] bits. Table 20-1.
PAGE 238
Timer Interface Module B (TIMB) 20.8.3 TIMB Counter Modulo Registers The read/write TIMB modulo registers contain the modulo value for the TIMB counter. When the TIMB counter reaches the modulo value, the overflow flag (TOF) becomes set and the TIMB counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TBMODH) inhibits the TOF bit and overflow interrupts until the low byte (TBMODL) is written. Reset sets the TIMB counter modulo registers.
PAGE 239
I/O Registers Register Name and Address Bit 7 Read: CH0F Write: 0 Reset: 0 TBSC0 — $0045 6 5 4 3 2 1 Bit 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 Register Name and Address Bit 7 TBSC1 — $0048 6 Read: CH1F Write: 0 Reset: 0 0 R = Reserved CH1IE 5 0 R 0 Figure 20-7.
PAGE 240
Timer Interface Module B (TIMB) When ELSxB:A = 00, this read/write bit selects the initial output level of the TBCHx pin once PWM, input capture or output compare operation is enabled (see Table 20-2). Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIMB status and control register (TBSC).
PAGE 241
I/O Registers TOVx — Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIMB counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIMB counter overflow. 0 = Channel x pin does not toggle on TIMB counter overflow.
PAGE 242
Timer Interface Module B (TIMB) Register Name and Address Read: Write: TBCH0H — $0046 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate after Reset Register Name and Address Read: Write: TBCH0L — $0047 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset: Indeterminate after Reset Register Name and Address Read: Write: TBCH1H — $0049 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit
PAGE 243
Chapter 21 Programmable Interrupt Timer (PIT) 21.1 Introduction This chapter describes the Programmable Interrupt Timer (PIT) which is a periodic interrupt timer whose counter is clocked internally via software programmable options. Figure 21-1 is a block diagram of the PIT. For further information regarding timers on M68HC08 family devices, please consult the HC08 Timer Reference Manual, TIM08RM/AD. 21.
PAGE 244
Programmable Interrupt Timer (PIT) Register Name Bit 7 Read: POF 6 5 4 3 0 0 2 1 Bit 0 PPS2 PPS1 PPS0 POIE PSTOP 0 0 1 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Reset: 0 0 0 0 0 0 0 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 PIT Status and Control Register (PSC) Write: 0 Reset: Read: PRST PIT Counter Register High (PCNTH) Wri
PAGE 245
PIT During Break Interrupts If PIT functions are not required during wait mode, reduce power consumption by stopping the PIT before executing the WAIT instruction. 21.5.2 Stop Mode The PIT is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the PIT counter. PIT operation resumes when the MCU exits stop mode after an external interrupt. 21.6 PIT During Break Interrupts A break interrupt stops the PIT counter.
PAGE 246
Programmable Interrupt Timer (PIT) Address: $004B Bit 7 Read: POF Write: 0 Reset: 0 6 5 POIE PSTOP 0 1 4 3 0 0 PRST 0 0 2 1 Bit 0 PPS2 PPS1 PPS0 0 0 0 = Unimplemented Figure 21-3. PIT Status and Control Register (PSC) POF — PIT Overflow Flag Bit This read/write flag is set when the PIT counter reaches the modulo value programmed in the PIT counter modulo registers. Clear POF by reading the PIT status and control register when POF is set and then writing a 0 to POF.
PAGE 247
I/O Registers Table 21-2. Prescaler Selection PPS[2:0] PIT Clock Source 000 Internal Bus Clock ÷1 001 Internal Bus Clock ÷ 2 010 Internal Bus Clock ÷ 4 011 Internal Bus Clock ÷ 8 100 Internal Bus Clock ÷ 16 101 Internal Bus Clock ÷ 32 110 Internal Bus Clock ÷ 64 111 Internal Bus Clock ÷ 64 21.7.2 PIT Counter Registers The two read-only PIT counter registers contain the high and low bytes of the value in the PIT counter.
PAGE 248
Programmable Interrupt Timer (PIT) 21.7.3 PIT Counter Modulo Registers The read/write PIT modulo registers contain the modulo value for the PIT counter. When the PIT counter reaches the modulo value the overflow flag (POF) becomes set and the PIT counter resumes counting from $0000 at the next timer clock. Writing to the high byte (PMODH) inhibits the POF bit and overflow interrupts until the low byte (PMODL) is written. Reset sets the PIT counter modulo registers.
PAGE 249
Chapter 22 Input/Output Ports 22.1 Introduction On the MC68HC908AZ60A and 64-pin MC68HC908AS60A, fifty bidirectional input/output (I/O) form seven parallel ports. On the52-pin MC68HC908AS60A, forty bidirectional input/output (I/O) form six parallel ports. All I/O pins are programmable as inputs or outputs. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
PAGE 250
Input/Output Ports 22.2 Port A Port A is an 8-bit general-purpose bidirectional I/O port. 22.2.1 Port A Data Register The port A data register contains a data latch for each of the eight port A pins. Address: Read: Write: $0000 Bit 7 6 5 4 3 2 1 Bit 0 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Reset: Unaffected by Reset Figure 22-2. Port A Data Register (PTA) PTA[7:0] — Port A Data Bits These read/write bits are software programmable.
PAGE 251
Port A READ DDRA ($0004) INTERNAL DATA BUS WRITE DDRA ($0004) DDRAx RESET WRITE PTA ($0000) PTAx PTAx READ PTA ($0000) Figure 22-4. Port A I/O Circuit When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 22-1 summarizes the operation of the port A pins. Table 22-1.
PAGE 252
Input/Output Ports 22.3 Port B Port B is an 8-bit special function port that shares all of its pins with the analog-to-digital converter. 22.3.1 Port B Data Register The port B data register contains a data latch for each of the eight port B pins. Address: Read: Write: $0001 Bit 7 6 5 4 3 2 1 Bit 0 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 ATD2 ATD1 ATD0 Reset: Alternative Functions: Unaffected by Reset ATD7 ATD6 ATD5 ATD4 ATD3 Figure 22-5.
PAGE 253
Port B 22.3.2 Data Direction Register B Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $0005 Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 22-6.
PAGE 254
Input/Output Ports 22.4 Port C Port C is an 6-bit general-purpose bidirectional I/O port. Note that PTC5 is only available on 64-pin package options. 22.4.1 Port C Data Register The port C data register contains a data latch for each of the six port C pins. Address: $0002 Bit 7 6 Read: 0 0 Write: R R R = Reserved 5 4 3 2 1 Bit 0 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 Reset: Unaffected by Reset Alternative Functions: MCLK Figure 22-8.
PAGE 255
Port C DDRC[5:0] — Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input NOTE Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 22-10 shows the port C I/O logic.
PAGE 256
Input/Output Ports 22.5 Port D Port D is an 8-bit general-purpose I/O port. Note that PTD7 is only available on 64-pin package options. 22.5.1 Port D Data Register Port D is a 8-bit special function port that shares seven of its pins with the analog to digital converter and two with the timer interface modules.
PAGE 257
Port D 22.5.2 Data Direction Register D Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $0007 Bit 7 6 5 4 3 2 1 Bit 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Figure 22-12.
PAGE 258
Input/Output Ports 22.6 Port E Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA), two of its pins with the serial communications interface module (SCI), and four of its pins with the serial peripheral interface module (SPI). 22.6.1 Port E Data Register The port E data register contains a data latch for each of the eight port E pins.
PAGE 259
Port E TACH[1:0] — Timer Channel I/O Bits The PTE3/TACH1–PTE2/TACH0 pins are the TIM input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0 pins are timer channel I/O pins or general-purpose I/O pins. (See 25.8.4 TIMA Channel Status and Control Registers). NOTE Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the TIM.
PAGE 260
Input/Output Ports Figure 22-16 shows the port E I/O logic. READ DDRE ($000C) INTERNAL DATA BUS WRITE DDRE ($000C) RESET DDREx WRITE PTE ($0008) PTEx PTEx READ PTE ($0008) Figure 22-16. Port E I/O Circuit When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
PAGE 261
Port F 22.7.1 Port F Data Register The port F data register contains a data latch for each of the seven port F pins. Address: $0009 Bit 7 Read: 0 Write: R 6 5 4 3 2 1 Bit 0 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 TACH4 TACH3 TACH2 Reset: Unaffected by Reset Alternative Function: TBCH1 R TBCH0 TACH5 = Reserved Figure 22-17. Port F Data Register (PTF) PTF[6:0] — Port F Data Bits These read/write bits are software programmable.
PAGE 262
Input/Output Ports DDRF[6:0] — Data Direction Register F Bits These read/write bits control port F data direction. Reset clears DDRF[6:0], configuring all port F pins as inputs. 1 = Corresponding port F pin configured as output 0 = Corresponding port F pin configured as input NOTE Avoid glitches on port F pins by writing to the port F data register before changing data direction register F bits from 0 to 1. Figure 22-19 shows the port F I/O logic.
PAGE 263
Port G 22.8 Port G Port G is a 3-bit special function port that shares all of its pins with the keyboard interrupt module (KBD). Note that Port G is only available on 64-pin package options. 22.8.1 Port G Data Register The port G data register contains a data latch for each of the three port G pins. Address: $000A Bit 7 6 5 4 3 Read: 0 0 0 0 0 Write: R R R R R Reset: 2 1 Bit 0 PTG2 PTG1 PTG0 KBD2 KBD1 KBD0 Unaffected by Reset Alternative Function: R = Reserved Figure 22-20.
PAGE 264
Input/Output Ports DDRG[2:0] — Data Direction Register G Bits These read/write bits control port G data direction. Reset clears DDRG[2:0], configuring all port G pins as inputs. 1 = Corresponding port G pin configured as output 0 = Corresponding port G pin configured as input NOTE Avoid glitches on port G pins by writing to the port G data register before changing data direction register G bits from 0 to 1. Figure 22-22 shows the port G I/O logic.
PAGE 265
Port H 22.9 Port H Port H is a 2-bit special function port that shares all of its pins with the keyboard interrupt module (KBD). Note that Port H is only available on 64-pin package options. 22.9.1 Port H Data Register The port H data register contains a data latch for each of the two port H pins. Address: $000B Bit 7 6 5 4 3 2 Read: 0 0 0 0 0 0 Write: R R R R R R Reset: 1 Bit 0 PTH1 PTH0 KBD4 KBD3 Unaffected by Reset Alternative Function: R = Reserved Figure 22-23.
PAGE 266
Input/Output Ports Figure 22-25 shows the port H I/O logic. READ DDRH ($000F) INTERNAL DATA BUS WRITE DDRH ($000F) RESET DDRHx WRITE PTH ($000B) PTHx PTHx READ PTH ($000B) Figure 22-25. Port H I/O Circuit When bit DDRHx is a logic 1, reading address $000B reads the PTHx data latch. When bit DDRHx is a logic 0, reading address $000B reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
PAGE 267
Chapter 23 MSCAN Controller (MSCAN08) 23.1 Introduction The MSCAN08 is the specific implementation of the MSCAN concept targeted for the Freescale M68HC08 Microcontroller Family. The module is a communication controller implementing the CAN 2.0 A/B protocol as defined in the BOSCH specification dated September 1991.
PAGE 268
MSCAN Controller (MSCAN08) 23.3 External Pins The MSCAN08 uses two external pins, one input (RxCAN) and one output (TxCAN). The TxCAN output pin represents the logic level on the CAN: 0 is for a dominant state, and 1 is for a recessive state. A typical CAN system with MSCAN08 is shown in Figure 23-1. CAN STATION 1 CAN NODE 1 CAN NODE 2 CAN NODE N MCU CAN CONTROLLER (MSCAN08) TXCAN RXCAN TRANSCEIVER CAN_H CAN_L C A N BUS Figure 23-1.
PAGE 269
Message Storage Above behavior cannot be achieved with a single transmit buffer. That buffer must be reloaded right after the previous message has been sent. This loading process lasts a definite amount of time and has to be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt.
PAGE 270
MSCAN Controller (MSCAN08) An overrun condition occurs when both the foreground and the background receive message buffers are filled with correctly received messages with accepted identifiers and another message is correctly received from the bus with an accepted identifier. The latter message will be discarded and an error interrupt with overrun indication will be generated if enabled.
PAGE 271
Identifier Acceptance Filter To transmit a message, the CPU08 has to identify an available transmit buffer which is indicated by a set transmit buffer empty (TXE) flag in the MSCAN08 transmitter flag register (CTFLG) (see 23.13.7 MSCAN08 Transmitter Flag Register). The CPU08 then stores the identifier, the control bits and the data content into one of the transmit buffers. Finally, the buffer has to be flagged ready for transmission by clearing the TXE flag.
PAGE 272
MSCAN Controller (MSCAN08) • • • Two identifier acceptance filters, each to be applied to a) the 14 most significant bits of the extended identifier plus the SRR and the IDE bits of CAN2.0B messages, or b) the 11 bits of the identifier plus the RTR and IDE bits of CAN 2.0A/B messages. Figure 23-4 shows how the 32-bit filter bank (CIDAR0-3, CIDMR0-3) produces filter 0 and 1 hits. Four identifier acceptance filters, each to be applied to the first eight bits of the identifier.
PAGE 273
Identifier Acceptance Filter ID28 IDR0 ID21 ID20 IDR1 ID10 IDR0 ID3 ID2 IDR1 AM7 CIDMR0 AM0 AC7 CIDAR0 AC0 ID15 ID14 IDE ID10 IDR2 ID7 ID6 IDR3 RTR IDR2 ID3 ID10 IDR3 ID3 ID ACCEPTED (FILTER 0 HIT) AM7 CIDMR1 AM0 AC7 CIDAR1 AC0 ID ACCEPTED (FILTER 1 HIT) AM7 CIDMR2 AM0 AC7 CIDAR2 AC0 ID ACCEPTED (FILTER 2 HIT) AM7 CIDMR3 AM0 AC7 CIDAR3 AC0 ID ACCEPTED (FILTER 3 HIT) Figure 23-5.
PAGE 274
MSCAN Controller (MSCAN08) 23.6 Interrupts The MSCAN08 supports four interrupt vectors mapped onto eleven different interrupt sources, any of which can be individually masked (for details see 23.13.5 MSCAN08 Receiver Flag Register (CRFLG), to 23.13.8 MSCAN08 Transmitter Control Register). • Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXE flags of the empty message buffers are set.
PAGE 275
Protocol Violation Protection 23.6.2 Interrupt Vectors The MSCAN08 supports four interrupt vectors as shown in Table 23-1. The vector addresses and the relative interrupt priority are dependent on the chip integration and to be defined. Table 23-1.
PAGE 276
MSCAN Controller (MSCAN08) . Table 23-2. MSCAN08 versus CPU Operating Modes CPU Mode MSCAN Mode STOP Power Down WAIT or RUN SLPAK = X(1) SFTRES = X Sleep SLPAK = 1 SFTRES = 0 Soft Reset SLPAK = 0 SFTRES = 1 Normal SLPAK = 0 SFTRES = 0 1. ‘X’ means don’t care. 23.8.1 MSCAN08 Sleep Mode The CPU can request the MSCAN08 to enter the low-power mode by asserting the SLPRQ bit in the module configuration register (see Figure 23-6).
PAGE 277
Low Power Modes During Sleep mode, the SLPAK flag is set. The application software should use SLPAK as a handshake indication for the request (SLPRQ) to go into Sleep mode. When in Sleep mode, the MSCAN08 stops its internal clocks. However, clocks to allow register accesses still run. If the MSCAN08 is in buss-off state, it stops counting the 128*11 consecutive recessive bits due to the stopped clocks. The TxCAN pin stays in recessive state. If RXF=1, the message can be read and RXF can be cleared.
PAGE 278
MSCAN Controller (MSCAN08) In Power Down mode, no registers can be accessed. MSCAN08 bus activity can wake the MCU from CPU Stop/MSCAN08 power-down mode. However, until the oscillator starts up and synchronisation is achieved the MSCAN08 will not respond to incoming data. 23.8.4 CPU Wait Mode The MSCAN08 module remains active during CPU wait mode. The MSCAN08 will stay synchronized to the CAN bus and generates transmit, receive, and error interrupts to the CPU, if enabled.
PAGE 279
Clock System CGMXCLK ÷2 OSC CGMOUT (TO SIM) BCS PLL ÷2 CGM MSCAN08 (2 * BUS FREQ.) ÷2 MSCANCLK PRESCALER (1 .. 64) CLKSRC Figure 23-7. Clocking Scheme The clock source bit (CLKSRC) in the MSCAN08 module control register (CMCR1) (see 23.13.1 MSCAN08 Module Control Register 0) defines whether the MSCAN08 is connected to the output of the crystal oscillator or to the PLL output. The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.
PAGE 280
MSCAN Controller (MSCAN08) • Time segment 2: This segment represents PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long. Bit rate= fTq No. of time quanta The synchronization jump width (SJW) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. The above parameters can be set by programming the bus timing registers, CBTR0–CBTR1, see 23.13.3 MSCAN08 Bus Timing Register 0 and 23.13.4 MSCAN08 Bus Timing Register 1).
PAGE 281
Memory Map Table 23-4. CAN Standard Compliant Bit Time Segment Settings Time Segment 1 TSEG1 Time Segment 2 TSEG2 Synchron. Jump Width SJW 5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3 23.11 Memory Map The MSCAN08 occupies 128 bytes in the CPU08 memory space.
PAGE 282
MSCAN Controller (MSCAN08) 23.12 Programmer’s Model of Message Storage This subsection details the organization of the receive and transmit message buffers and the associated control registers. For reasons of programmer interface simplification, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13-byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers.
PAGE 283
Programmer’s Model of Message Storage Addr Register Read: $05b0 IDR0 $05b1 IDR1 $05b2 IDR2 $05b3 IDR3 $05b4 DSR0 $05b5 DSR1 $05b6 DSR2 $05b7 DSR3 $05b8 DSR4 $05b9 DSR5 $05bA DSR6 $05bB DSR7 $05bC DLR Write: Read: Write: Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR DB7 DB6 DB5 DB4 DB3 DB2
PAGE 284
MSCAN Controller (MSCAN08) IDE — ID Extended This flag indicates whether the extended or standard identifier format is applied in this buffer. In case of a receive buffer, the flag is set as being received and indicates to the CPU how to process the buffer identifier registers. In case of a transmit buffer, the flag indicates to the MSCAN08 what type of identifier to send.
PAGE 285
Programmer’s Model of Message Storage 23.12.4 Data Segment Registers (DSRn) The eight data segment registers contain the data to be transmitted or received. The number of bytes to be transmitted or being received is determined by the data length code in the corresponding DLR. 23.12.5 Transmit Buffer Priority Registers Address: Read: Write: Reset: $05bD Bit 7 6 5 4 3 2 1 Bit 0 PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 Unaffected by Reset Figure 23-13.
PAGE 286
MSCAN Controller (MSCAN08) 23.13 Programmer’s Model of Control Registers The programmer’s model has been laid out for maximum simplicity and efficiency. Figure 23-14 gives an overview on the control register block of the MSCAN08.
PAGE 287
Programmer’s Model of Control Registers 23.13.1 MSCAN08 Module Control Register 0 Address: Read: $0500 Bit 7 6 5 4 0 0 0 SYNCH 0 0 0 0 Write: Reset: 3 TLNKEN 0 2 SLPAK 0 1 Bit 0 SLPRQ SFTRES 0 1 = Unimplemented Figure 23-15. Module Control Register 0 (CMCR0) SYNCH — Synchronized Status This bit indicates whether the MSCAN08 is synchronized to the CAN bus and as such can participate in the communication process.
PAGE 288
MSCAN Controller (MSCAN08) 23.13.2 MSCAN08 Module Control Register 1 Address: Read: $0501 Bit 7 6 5 4 3 0 0 0 0 0 2 1 Bit 0 LOOPB WUPM CLKSRC 0 0 0 Write: Reset: 0 0 0 0 0 = Unimplemented Figure 23-16. Module Control Register (CMCR1) LOOPB — Loop Back Self-Test Mode When this bit is set, the MSCAN08 performs an internal loop back which can be used for self-test operation: the bit stream output of the transmitter is fed back to the receiver internally.
PAGE 289
Programmer’s Model of Control Registers 23.13.3 MSCAN08 Bus Timing Register 0 Address: $0502 Bit 7 6 5 4 3 2 1 Bit 0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 23-17.
PAGE 290
MSCAN Controller (MSCAN08) 23.13.4 MSCAN08 Bus Timing Register 1 Address: Read: Write: Reset: $0503 Bit 7 6 5 4 3 2 1 Bit 0 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0 0 0 0 0 0 0 0 Figure 23-18. Bus Timing Register 1 (CBTR1) SAMP — Sampling This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority rule.
PAGE 291
Programmer’s Model of Control Registers 23.13.5 MSCAN08 Receiver Flag Register (CRFLG) All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. A flag can be cleared only when the condition which caused the setting is valid no more. Writing a 0 has no effect on the flag setting. Every flag has an associated interrupt enable flag in the CRIER register. A hard or soft reset will clear the register.
PAGE 292
MSCAN Controller (MSCAN08) TERRIF — Transmitter Error Passive Interrupt Flag This flag is set when the MSCAN08 goes into error passive status due to the Transmit Error counter exceeding 127 and the Bus-off interrupt flag is not set(1). If not masked, an Error interrupt is pending while this flag is set. 1 = MSCAN08 went into transmit error passive status. 0 = No transmit error passive status has been reached.
PAGE 293
Programmer’s Model of Control Registers 23.13.6 MSCAN08 Receiver Interrupt Enable Register Address: Read: Write: Reset: $0505 Bit 7 6 5 4 3 2 1 Bit 0 WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE 0 0 0 0 0 0 0 0 Figure 23-20. Receiver Interrupt Enable Register (CRIER) WUPIE — Wakeup Interrupt Enable 1 = A wakeup event will result in a wakeup interrupt. 0 = No interrupt will be generated from this event.
PAGE 294
MSCAN Controller (MSCAN08) 23.13.7 MSCAN08 Transmitter Flag Register The Abort Acknowledge flags are read only. The Transmitter Buffer Empty flags are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag setting. The Transmitter Buffer Empty flags each have an associated interrupt enable bit in the CTCR register. A hard or soft reset will resets the register.
PAGE 295
Programmer’s Model of Control Registers 23.13.8 MSCAN08 Transmitter Control Register Address: $0507 Bit 7 Read: 0 Write: Reset: 0 6 5 4 ABTRQ2 ABTRQ1 ABTRQ0 0 0 0 3 0 0 2 1 Bit 0 TXEIE2 TXEIE1 TXEIE0 0 0 0 = Unimplemented Figure 23-22. Transmitter Control Register (CTCR) ABTRQ2–ABTRQ0 — Abort Request The CPU sets an ABTRQx bit to request that an already scheduled message buffer (TXE = 0) be aborted.
PAGE 296
MSCAN Controller (MSCAN08) 23.13.9 MSCAN08 Identifier Acceptance Control Register Address: Read: $0508 Bit 7 6 0 0 0 0 Write: Reset: 5 4 IDAM1 IDAM0 0 0 3 2 1 Bit 0 0 0 IDHIT1 IDHIT0 0 0 0 0 = Unimplemented Figure 23-23. Identifier Acceptance Control Register (CIDAC) IDAM1–IDAM0— Identifier Acceptance Mode The CPU sets these flags to define the identifier acceptance filter organization (see 23.5 Identifier Acceptance Filter). Table 23-9 summarizes the different settings.
PAGE 297
Programmer’s Model of Control Registers 23.13.10 MSCAN08 Receive Error Counter Address: Read: $050E Bit 7 6 5 4 3 2 1 Bit 0 RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 23-24. Receiver Error Counter (CRXERR) This register reflects the status of the MSCAN08 receive error counter. The register is read only. 23.13.
PAGE 298
MSCAN Controller (MSCAN08) 23.13.12 MSCAN08 Identifier Acceptance Registers On reception each message is written into the background receive buffer. The CPU is only signalled to read the message, however, if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message will be overwritten by the next message (dropped). The acceptance registers of the MSCAN08 are applied on the IDR0 to IDR3 registers of incoming messages in a bit by bit manner.
PAGE 299
Programmer’s Model of Control Registers 23.13.13 MSCAN08 Identifier Mask Registers (CIDMR0-3) The identifier mask registers specify which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. For standard identifiers it is required to program the last three bits (AM2-AM0) in the mask register CIDMR1 to ‘don’t care’.
PAGE 300
MSCAN Controller (MSCAN08) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 301
Chapter 24 Keyboard Module (KBI) 24.1 Introduction The keyboard interrupt module (KBD) provides five independently maskable external interrupt pins. This module is only available on 64-pin package options. 24.2 Features KBD features include: • Five Keyboard Interrupt Pins with Separate Keyboard Interrupt Enable Bits and One Keyboard Interrupt Mask • Hysteresis Buffers • Programmable Edge-Only or Edge- and Level- Interrupt Sensitivity • Automatic Interrupt Acknowledge • Exit from Low-Power Modes 24.
PAGE 302
Keyboard Module (KBI) 302 INTERNAL BUS KBD0 VECTOR FETCH DECODER ACKK VDD KEYF Freescale Semiconductor MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 RESET . TO PULLUP ENABLE D CLR Q SYNCHRONIZER . CK KB0IE . KEYBOARD INTERRUPT FF KBD4 KEYBOARD INTERRUPT REQUEST IMASKK MODEK TO PULLUP ENABLE KB4IE Figure 24-1.
PAGE 303
Keyboard Initialization If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register (KBSCR).
PAGE 304
Keyboard Module (KBI) Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRG bits in data direction register G. 2. Configure the keyboard pins as outputs by setting the appropriate DDRH bits in data direction register H. 3. Write logic 1s to the appropriate port G and port H data register bits. 4. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 24.
PAGE 305
I/O Registers 24.7.1 Keyboard Status and Control Register The keyboard status and control register: • Flags keyboard interrupt requests • Acknowledges keyboard interrupt requests • Masks keyboard interrupt requests • Controls keyboard interrupt triggering sensitivity Address: $001B Read: Bit 7 6 5 4 3 2 0 0 0 0 KEYF 0 Write: Reset: ACKK 0 0 0 0 0 0 1 Bit 0 IMASKK MODEK 0 0 = Unimplemented Figure 24-3.
PAGE 306
Keyboard Module (KBI) 24.7.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port G and each port H pin to operate as a keyboard interrupt pin. Address: $0021 Read: Bit 7 6 5 0 0 0 0 0 0 Write: Reset: 4 3 2 1 Bit 0 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 = Unimplemented Figure 24-4.
PAGE 307
Chapter 25 Timer Interface Module A (TIMA) 25.1 Introduction This section describes the timer interface module (TIMA). The TIMA is a 6-channel timer that provides a timing reference with input capture, output compare and pulse-width-modulation functions. Figure 25-1 is a block diagram of the TIMA. For further information regarding timers on M68HC08 family devices, please consult the HC08 Timer Reference Manual, TIM08RM/AD. 25.
PAGE 308
Timer Interface Module A (TIMA) TCLK PTD6/ATD14/TACLK PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 ELS0B ELS0A TOV0 CH0MAX 16-BIT COMPARATOR TCH0H:TCH0L CH0F 16-BIT LATCH MS0A CHANNEL 1 ELS1B MS0B ELS1A TOV1 CH1MAX 16-BIT COMPARATOR TCH1H:TCH1L CH0IE CH1F 16-BIT LATCH CH1IE MS1A CHANNEL 2 ELS2B ELS2A TOV2 CH2MAX 16-BIT COMPARATOR TCH2H:TCH2L CH2F 16-BIT LATCH MS2A CHANNE
PAGE 309
Functional Description Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 TOF TOIE TSTOP TRST 0 PS2 PS1 PS0 R R R R R R R R $0020 TIMA Status/Control Register (TASC) $0021 Reserved $0022 TIMA Counter Register High (TACNTH) Bit 15 14 13 12 11 10 9 Bit 8 $0023 TIMA Counter Register Low (TACNTL) Bit 7 6 5 4 3 2 1 Bit 0 $0024 TIMA Counter Modulo Reg. High (TAMODH) Bit 15 14 13 12 11 10 9 Bit 8 $0025 TIMA Counter Modulo Reg.
PAGE 310
Timer Interface Module A (TIMA) 25.3.1 TIMA Counter Prescaler The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin, PTD6/ATD14/TACLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMA status and control register select the TIMA clock source. 25.3.2 Input Capture An input capture function has three basic parts: edge select logic, an input capture latch and a 16-bit counter.
PAGE 311
Functional Description 25.3.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 25.3.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIMA channel registers. An unsynchronized write to the TIMA channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods.
PAGE 312
Timer Interface Module A (TIMA) PTF2 pin. Writing to the TIMA channel 5 registers enables the TIMA channel 5 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (4 or 5) that control the output are the ones written to last. TASC4 controls and monitors the buffered output compare function and TIMA channel 5 status and control register (TASC5) is unused.
PAGE 313
Functional Description 25.3.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 25.3.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the TIMA channel registers. An unsynchronized write to the TIMA channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods.
PAGE 314
Timer Interface Module A (TIMA) (2 or 3) that control the pulse width are the ones written to last. TASC2 controls and monitors the buffered PWM function and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin. Channels 4 and 5 can be linked to form a buffered PWM channel whose output appears on the PTF2 pin.
PAGE 315
Interrupts Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMA channel 0 registers (TACH0H–TACH0L) initially control the buffered PWM output. TIMA status control register 0 (TASC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIMA channel 2 registers (TACH2H–TACH2L) initially control the buffered PWM output.
PAGE 316
Timer Interface Module A (TIMA) 25.6 TIMA During Break Interrupts A break interrupt stops the TIMA counter and inhibits input captures. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state (see 9.7.3 SIM Break Flag Control Register).
PAGE 317
I/O Registers 25.8 I/O Registers These I/O registers control and monitor TIMA operation: • TIMA status and control register (TASC) • TIMA control registers (TACNTH–TACNTL) • TIMA counter modulo registers (TAMODH–TAMODL) • TIMA channel status and control registers (TASC0, TASC1, TASC2, TASC3, TASC4 and TASC5) • TIMA channel registers (TACH0H–TACH0L, TACH1H–TACH1L, TACH2H–TACH2L, TACH3H–TACH3L, TACH4H–TACH4L and TACH5H–TACH5L) 25.8.
PAGE 318
Timer Interface Module A (TIMA) NOTE Do not set the TSTOP bit before entering wait mode if the TIMA is required to exit wait mode. Also, when the TSTOP bit is set and input capture mode is enabled, input captures are inhibited until TSTOP is cleared. When using the TSTOP to stop the timer counter, see if any timer flags are set. If a timer flag is set, it must be cleared by clearing the TSTOP, then clearing the flag, then setting the TSTOP again.
PAGE 319
I/O Registers Register Name and Address Read: TACNTH — $0022 Bit 7 6 5 4 3 2 1 Bit 0 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 0 0 0 0 0 0 0 0 Write: Reset: Register Name and Address Read: TACNTL — $0023 Bit 7 6 5 4 3 2 1 Bit 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 25-5. TIMA Counter Registers (TACNTH and TACNTL) 25.8.
PAGE 320
Timer Interface Module A (TIMA) 25.8.
PAGE 321
I/O Registers Register Name and Address Bit 7 Read: CH5F Write: 0 Reset: 0 R TASC5 — $0035 6 CH5IE 0 5 0 R 0 4 3 2 1 Bit 0 MS5A ELS5B ELS5A TOV5 CH5MAX 0 0 0 0 0 = Reserved Figure 25-7. TIMA Channel Status and Control Registers (TASC0–TASC5) (Continued) CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin.
PAGE 322
Timer Interface Module A (TIMA) When ELSxB:A = 00, this read/write bit selects the initial output level of the TACHx pin once PWM, output compare mode or input capture mode is enabled. See Table 25-2. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIMA status and control register (TASC).
PAGE 323
I/O Registers TOVx — Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIMA counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIMA counter overflow. 0 = Channel x pin does not toggle on TIMA counter overflow.
PAGE 324
Timer Interface Module A (TIMA) Register Name and Address Read: Write: TACH0L — $0028 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset: Indeterminate after Reset Register Name and Address Read: Write: TACH1H — $002A Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate after Reset Register Name and Address Read: Write: TACH1L — $002B Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4
PAGE 325
I/O Registers Register Name and Address Read: Write: TACH4H — $0033 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate after Reset Register Name and Address Read: Write: TACH4L — $0034 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset: Indeterminate after Reset Register Name and Address Read: Write: TACH5H — $0036 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
PAGE 326
Timer Interface Module A (TIMA) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 327
Chapter 26 Analog-to-Digital Converter (ADC) 26.1 Introduction This section describes the analog-to-digital converter (ADC-15). The ADC is an 8-bit analog-to-digital converter. For further information regarding analog-to-digital converters on Freescale microcontrollers, please consult the HC08 ADC Reference Manual, ADCRM/AD. 26.
PAGE 328
Analog-to-Digital Converter (ADC) INTERNAL DATA BUS READ DDRB/DDRB WRITE DDRB/DDRD RESET WRITE PTB/PTD DISABLE DDRBx/DDRDx PTBx/PTDx PTBx/PTDx ADC CHANNEL x READ PTB/PTD DISABLE ADC DATA REGISTER INTERRUPT LOGIC AIEN CONVERSION COMPLETE ADC VOLTAGE IN ADCVIN ADC CHANNEL SELECT ADCH[4:0] COCO ADC CLOCK CGMXCLK BUS CLOCK CLOCK GENERATOR ADIV[2:0] ADICLK Figure 26-1. ADC Block Diagram 26.3.
PAGE 329
Interrupts 26.3.2 Voltage Conversion When the input voltage to the ADC equals VREFH (see 28.1.6 ADC Characteristics), the ADC converts the signal to $FF (full scale). If the input voltage equals VSSA, the ADC converts it to $00. Input voltages between VREFH and VSSA are a straight-line linear conversion. Conversion accuracy of all other input voltages is not guaranteed. Avoid current injection on unused ADC inputs to prevent potential conversion error.
PAGE 330
Analog-to-Digital Converter (ADC) 26.5 Low-Power Modes The following subsections describe the low-power modes. 26.5.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits in the ADC status and control register before executing the WAIT instruction. 26.5.
PAGE 331
I/O Registers 26.7.1 ADC Status and Control Register The following paragraphs describe the function of the ADC status and control register. Address: $0038 Read: COCO Write: R Reset: Bit 7 6 5 4 3 2 1 Bit 0 AIEN ADCO CH4 CH3 CH2 CH1 CH0 0 0 0 1 1 1 1 1 R = Reserved Figure 26-2. ADC Status and Control Register (ADSCR) COCO — Conversions Complete Bit When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is completed.
PAGE 332
Analog-to-Digital Converter (ADC) Table 26-1.
PAGE 333
I/O Registers 26.7.3 ADC Input Clock Register This register selects the clock frequency for the ADC. Address: $003A Bit 7 Read: Write: Reset: 6 5 4 ADIV2 ADIV1 ADIV0 ADICLK 0 0 0 0 3 2 1 Bit 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 26-4. ADC Input Clock Register (ADICLK) ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock.
PAGE 334
Analog-to-Digital Converter (ADC) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 335
Chapter 27 Byte Data Link Controller (BDLC) 27.1 Introduction The byte data link controller (BDLC) provides access to an external serial communication multiplex bus, operating according to the Society of Automotive Engineers (SAE) J1850 protocol. The BDLC-D is only available on the MC68HC908AS60A. 27.
PAGE 336
Byte Data Link Controller (BDLC) TO CPU CPU INTERFACE PROTOCOL HANDLER MUX INTERFACE PHYSICAL INTERFACE BDLC TO J1850 BUS Figure 27-1. BDLC Block Diagram Addr.
PAGE 337
Functional Description 27.3.1 BDLC Operating Modes The BDLC has five main modes of operation which interact with the power supplies, pins, and the remainder of the MCU as shown in Figure 27-3.
PAGE 338
Byte Data Link Controller (BDLC) 27.3.1.3 Run Mode This mode is entered from the reset mode after all MCU reset sources are no longer asserted. Run mode is entered from the BDLC wait mode whenever activity is sensed on the J1850 bus. Run mode is entered from the BDLC stop mode whenever network activity is sensed, although messages will not be received properly until the clocks have stabilized and the CPU is in run mode also. In this mode, normal network operation takes place.
PAGE 339
BDLC MUX Interface 27.4 BDLC MUX Interface The MUX interface is responsible for bit encoding/decoding and digital noise filtering between the protocol handler and the physical interface. TO CPU CPU INTERFACE PROTOCOL HANDLER MUX INTERFACE PHYSICAL INTERFACE BDLC TO J1850 BUS Figure 27-4. BDLC Block Diagram 27.4.1 Rx Digital Filter The receiver section of the BDLC includes a digital low pass filter to remove narrow noise pulses from the incoming message.
PAGE 340
Byte Data Link Controller (BDLC) The counter will increment if the input data sample is high but decrement if the input sample is low. Therefore, the counter will thus progress either up toward 15 if, on average, the BDRxD signal remains high or progress down toward 0 if, on average, the BDRxD signal remains low.
PAGE 341
BDLC MUX Interface DATA IDLE SOF PRIORITY (DATA0) MESSAGE ID (DATA1) DATAN CRC E O D OPTIONAL N B IFR EOF I F S IDLE . J1850 Bus Message Format (VPW) SOF — Start-of-Frame Symbol All messages transmitted onto the J1850 bus must begin with a long-active 200-μs period SOF symbol. This indicates the start of a new message transmission. The SOF symbol is not used in the CRC calculation.
PAGE 342
Byte Data Link Controller (BDLC) IFR — In-Frame Response Bytes The IFR section of the J1850 message format is optional. Users desiring further definition of in-frame response should review the SAE J1850 — Class B Data Communications Network Interface specification. EOF — End-of-Frame Symbol This symbol is a long 280-μs passive period on the J1850 bus and is longer than an end-of-data (EOD) symbol, which signifies the end of a message.
PAGE 343
BDLC MUX Interface If the BDLC detects a BREAK symbol while receiving a message, it treats the BREAK as a reception error and sets the invalid symbol flag in the BSVR, also ignoring the frame it was receiving. If while receiving a message in 4X mode, the BDLC detects a BREAK symbol, it treats the BREAK as a reception error, sets the invalid symbol flag, and exits 4X mode (for example, the RX4XE bit in BCR2 is cleared automatically).
PAGE 344
Byte Data Link Controller (BDLC) ACTIVE 128 μs OR 64 μs OR 64 μs PASSIVE (A) LOGIC 0 ACTIVE 128 μs PASSIVE (B) LOGIC 1 ACTIVE ≥ 240 μs 200 μs 200 μs PASSIVE (C) BREAK (D) START OF FRAME (E) END OF DATA 300 μs ACTIVE 280 μs 20 μs IDLE > 300 μs PASSIVE (F) END OF FRAME (G) INTER-FRAME SEPARATION (H) IDLE Figure 27-6.
PAGE 345
BDLC MUX Interface Idle An idle is defined as a passive period greater than 300 μs in length. 27.4.4 J1850 VPW Valid/Invalid Bits and Symbols The timing tolerances for receiving data bits and symbols from the J1850 bus have been defined to allow for variations in oscillator frequencies. In many cases the maximum time allowed to define a data bit or symbol is equal to the minimum time allowed to define another data bit or symbol.
PAGE 346
Byte Data Link Controller (BDLC) Valid Passive Logic 0 See Figure 27-7 (2). If the passive-to-active received transition beginning the next data bit (or symbol) occurs between a and b, the current bit would be considered a logic 0. Valid Passive Logic 1 See Figure 27-7 (3). If the passive-to-active received transition beginning the next data bit (or symbol) occurs between b and c, the current bit would be considered a logic 1. Valid EOD Symbol See Figure 27-7 (4).
PAGE 347
BDLC MUX Interface 200 μs 128 μs 64 μs ACTIVE (1) INVALID ACTIVE BIT PASSIVE a ACTIVE (2) VALID ACTIVE LOGIC 1 PASSIVE a b ACTIVE (3) VALID ACTIVE LOGIC 0 PASSIVE b c ACTIVE (4) VALID SOF SYMBOL PASSIVE c d Figure 27-9. J1850 VPW Received Active Symbol Times Valid Active Logic 1 In Figure 27-9 (2), if the active-to-passive received transition beginning the next data bit (or symbol) occurs between a and b, the current bit would be considered a logic 1.
PAGE 348
Byte Data Link Controller (BDLC) 240 μs ACTIVE (2) VALID BREAK SYMBOL PASSIVE e Figure 27-10. J1850 VPW Received BREAK Symbol Times 27.4.5 Message Arbitration Message arbitration on the J1850 bus is accomplished in a non-destructive manner, allowing the message with the highest priority to be transmitted, while any transmitters which lose arbitration simply stop transmitting and wait for an idle bus to begin transmitting again.
PAGE 349
BDLC Protocol Handler Since a logic 0 dominates a logic 1, the message with the lowest value will have the highest priority and will always win arbitration. For instance, a message with priority 000 will win arbitration over a message with priority 011. This method of arbitration will work no matter how many bits of priority encoding are contained in the message.
PAGE 350
Byte Data Link Controller (BDLC) 27.5.1 Protocol Architecture The protocol handler contains the state machine, Rx shadow register, Tx shadow register, Rx shift register, Tx shift register, and loopback multiplexer as shown in Figure 27-13.
PAGE 351
BDLC Protocol Handler Once the Tx shift register has completed its shifting operation for the current byte, the data byte in the Tx shadow register is loaded into the Tx shift register. After this transfer takes place, the Tx shadow register is ready to accept new data from the CPU when TDRE flag in BSVR is set. 27.5.4 Digital Loopback Multiplexer The digital loopback multiplexer connects RxD to either BDTxD or BDRxD, depending on the state of the DLOOP bit in the BCR2 register (see 27.6.
PAGE 352
Byte Data Link Controller (BDLC) CRC Error A cyclical redundancy check (CRC) error is detected when the data bytes and CRC byte of a received message are processed and the CRC calculation result is not equal to $C4. The CRC code will detect any single and 2-bit errors, as well as all 8-bit burst errors and almost all other types of errors. The CRC error flag ($18 in BSVR) is set when a CRC error is detected. (See 27.6.4 BDLC State Vector Register.
PAGE 353
BDLC CPU Interface 27.5.5.5 Summary Table 27-1. BDLC J1850 Bus Error Summary Error Condition BDLC Function Transmission Error For invalid bits or framing symbols on non-byte boundaries, invalid symbol interrupt will be generated. BDLC stops transmission. Cyclical Redundancy Check (CRC) Error CRC error interrupt will be generated. The BDLC will wait for SOF. Invalid Symbol: BDLC Receives Invalid Bits (Noise) The BDLC will abort transmission immediately. Invalid symbol interrupt will be generated.
PAGE 354
Byte Data Link Controller (BDLC) 27.6.1 BDLC Analog and Roundtrip Delay Register This register programs the BDLC to compensate for various delays of different external transceivers. The default delay value is16 μs. Timing adjustments from 9 μs to 24 μs in steps of 1 μs are available. The BARD register can be written only once after each reset, after which they become read-only bits. The register may be read at any time.
PAGE 355
BDLC CPU Interface Table 27-2. BDLC Transceiver Delay (Continued) BARD Offset Bits B0[3:0] Corresponding Expected Transceiver’s Delays (μs) 1000 17 1001 18 1010 19 1011 20 1100 21 1101 22 1110 23 1111 24 27.6.2 BDLC Control Register 1 This register is used to configure and control the BDLC. Address: $003C Bit 7 Read: Write: Reset: 6 5 4 IMSG CLKS R1 R0 1 1 1 0 R = Reserved 3 2 0 0 R R 0 0 1 Bit 0 IE WCM 0 0 Figure 27-16.
PAGE 356
Byte Data Link Controller (BDLC) . Table 27-3. BDLC Rate Selection fXCLK Frequency R1 R0 Division fBDLC 1.049 MHz 0 0 1 1.049 MHz 2.097 MHz 0 1 2 1.049 MHz 4.194 MHz 1 0 4 1.049 MHz 8.389 MHz 1 1 8 1.049 MHz 1.000 MHz 0 0 1 1.00 MHz 2.000 MHz 0 1 2 1.00 MHz 4.000 MHz 1 0 4 1.00 MHz 8.000 MHz 1 1 8 1.00 MHz IE— Interrupt Enable Bit This bit determines whether the BDLC will generate CPU interrupt requests in run mode.
PAGE 357
BDLC CPU Interface the off-chip analog transceiver is no longer in loopback mode, the BDLC waits for an EOF symbol before attempting to transmit. 1 = Input to the analog physical interface’s final drive stage is looped back to the BDLC receiver. The J1850 bus is not driven. 0 = The J1850 bus will be driven by the BDLC.
PAGE 358
Byte Data Link Controller (BDLC) TSIFR, TMIFR1, and TMIFR0 — Transmit In-Frame Response Control Bits These three bits control the type of in-frame response being sent. The programmer should not set more than one of these control bits to a 1 at any given time. However, if more than one of these three control bits are set to 1, the priority encoding logic will force these register bits to a known value as shown in Table 27-4.
PAGE 359
BDLC CPU Interface TSIFR — Transmit Single Byte IFR with No CRC (Type 1 or 2) Bit The TSIFR bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR, $003F) as a single byte IFR with no CRC. Typically, the byte transmitted is a unique identifier or address of the transmitting (responding) node. See Figure 27-18.
PAGE 360
Byte Data Link Controller (BDLC) If the programmer attempts to set the TMIFR1 bit immediately after the EOD symbol has been received from the bus, the TMIFR1 bit will remain in the reset state, and no attempt will be made to transmit an IFR byte. If a loss of arbitration occurs when the BDLC is transmitting any byte of a multiple byte IFR, the BDLC will go to the loss of arbitration state, set the appropriate flag, and cease transmission.
PAGE 361
BDLC CPU Interface 27.6.4 BDLC State Vector Register This register is provided to substantially decrease the CPU overhead associated with servicing interrupts while under operation of a multiplex protocol. It provides an index offset that is directly related to the BDLC’s current state, which can be used with a user-supplied jump table to rapidly enter an interrupt service routine. This eliminates the need for the user to maintain a duplicate state machine in software.
PAGE 362
Byte Data Link Controller (BDLC) Upon receiving a BDLC interrupt, the user can read the value within the BSVR, transferring it to the CPU’s index register. The value can then be used to index into a jump table, with entries four bytes apart, to quickly enter the appropriate service routine.
PAGE 363
Low-Power Modes The BDR is double buffered via a transmit shadow register and a receive shadow register. After the byte in the transmit shift register has been transmitted, the byte currently stored in the transmit shadow register is loaded into the transmit shift register. Once the transmit shift register has shifted the first bit out, the TDRE flag is set, and the shadow register is ready to accept the next data byte. The receive shadow register works similarly.
PAGE 364
Byte Data Link Controller (BDLC) If this mode is entered while the BDLC is receiving a message, the first subsequent received edge will cause the BDLC to wake up immediately, generate a CPU interrupt request, and wait for the BDLC internal operating clocks to restart and stabilize before normal communications can resume. Therefore, the BDLC is not guaranteed to receive that message correctly. NOTE It is important to ensure all transmissions are complete or aborted prior to putting the BDLC into stop mode.
PAGE 365
Chapter 28 Electrical Specifications 28.1 Electrical Specifications 28.1.1 Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 28.1.4 5.0 Volt DC Electrical Characteristics for guaranteed operating conditions. Rating(1) Symbol Value Unit Supply Voltage VDD –0.3 to +6.0 V Input Voltage VIN VSS –0.3 to VDD +0.
PAGE 366
Electrical Specifications 28.1.2 Functional Operating Range Rating Operating Temperature Range(1) Operating Voltage Range Symbol Value Unit TA –40 to TA(MAX) °C VDD 5.0 ± 0.5 V 1. TA(MAX) = 125°C for part suffix MFU/MFN TA(MAX) = 105°C for part suffix VFU/VFN TA(MAX) = 85°C for part suffix CFU/CFN NOTE For applications which use the LVI, Freescale guarantees the functionality of the device down to the LVI trip point (VLVI) within the constraints outlined in Chapter 16 Low-Voltage Inhibit (LVI).
PAGE 367
Electrical Specifications 28.1.4 5.0 Volt DC Electrical Characteristics Characteristic(1) Output High Voltage (ILOAD = –2.0 mA) All Ports (ILOAD = –5.0 mA) All Ports Total source current Output Low Voltage (ILOAD = 1.6 mA) All Ports (ILOAD = 10.
PAGE 368
Electrical Specifications 28.1.5 Control Timing Characteristic(1) Symbol Min Max Unit fBUS — 8.4 MHz RST Pulse Width Low tRL 1.5 — tcyc IRQ Interrupt Pulse Width Low (Edge-Triggered) tILHI 1.5 — tcyc IRQ Interrupt Pulse Period tILIL Note 4 — tcyc tTH, tTL tTLTL 2 Note(4) — — tcyc tWUP 2 5 μs Bus Operating Frequency (4.5–5.5 V — VDD Only) 16-Bit Timer(2) Input Capture Pulse Width(3) Input Capture Period MSCAN Wake-up Filter Pulse Width(5) 1. VDD = 5.0 Vdc ± 0.
PAGE 369
Electrical Specifications 28.1.7 5.0 Vdc ± 0.
PAGE 370
Electrical Specifications SS (INPUT) SS pin of master held high. 1 SCK (CPOL = 0) (OUTPUT) NOTE SCK (CPOL = 1) (OUTPUT) NOTE 5 4 5 4 6 MISO (INPUT) MSB IN BITS 6–1 10 11 MOSI (OUTPUT) MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT 13 12 NOTE: This first clock edge is generated internally, but is not seen at the SCK pin. a) SPI Master Timing (CPHA = 0) SS (INPUT) SS pin of master held high.
PAGE 371
Electrical Specifications SS (INPUT) 3 1 SCK (CPOL = 0) (INPUT) 11 5 4 2 SCK (CPOL = 1) (INPUT) 5 4 9 8 MISO (INPUT) SLAVE MSB OUT 6 MOSI (OUTPUT) BITS 6–1 7 NOTE 11 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN NOTE: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 5 4 2 3 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) MOSI (INPUT) 5 4 10 NOTE 9 SLAVE MSB OUT 6 7 BITS 6–1 11 10 MSB IN SLAVE LSB OUT BITS 6–1
PAGE 372
Electrical Specifications 28.1.8 CGM Operating Conditions Characteristic Symbol Min Typ Max Unit VDDA VDD–0.3 — VDD+0.3 V VSSA VSS–0.3 — VSS+0.3 V Crystal Reference Frequency fCGMRCLK 1 4.9152 8 MHz Module Crystal Reference Frequency fCGMXCLK — 4.9152 — MHz fNOM — 4.9152 — MHz VCO Center-of-Range Frequency fCGMVRS 4.9152 — Note(1) MHz VCO Operating Frequency fCGMVCLK 4.9152 — 32.0 Operating Voltage Range Nom. Multiplier Comments Same Frequency as fCGMRCLK 1.
PAGE 373
Electrical Specifications 28.1.10 CGM Acquisition/Lock Time Information Description(1) Symbol Min Typ(2) Max(2) Unit Manual Mode Time to Stable tACQ — (8 x VDDA) / (fCGMXCLK x KACQ) — s If CF Chosen Correctly Manual Stable to Lock Time tAL — (4 x VDDA) / (fCGMXCLK x KTRK) — s If CF Chosen Correctly Manual Acquisition Time tLOCK — tACQ+tAL — s Tracking Mode Entry Frequency Tolerance DTRK 0 — ± 3.6 % Acquisition Mode Entry Frequency Tolerance DUNT ± 6.3 — ± 7.
PAGE 374
Electrical Specifications 28.1.11 Timer Module Characteristics Characteristic Input Capture Pulse Width Input Clock Pulse Width Symbol Min Max Unit tTIH, tTIL 125 — ns tTCH, tTCL (1/fOP) + 5 — ns Symbol Min Max Unit VRDR 0.7 — V 28.1.12 RAM Memory Characteristics Characteristic RAM Data Retention Voltage 28.1.
PAGE 375
Electrical Specifications 28.1.14 FLASH Memory Characteristics Characteristic Symbol Min Max Unit — 1 — MHz FLASH Read Bus Clock Frequency fREAD(1) 32K 8.
PAGE 376
Electrical Specifications 28.1.
PAGE 377
Electrical Specifications 13 1 14 10 12 SOF 0 0 11 1 15 0 EOD 16 EOF 18 BRK Figure 28-3. BDLC Variable Pulse Width Modulation (VPW) Symbol Timing 28.1.17 BDLC Transmitter DC Electrical Characteristics Characteristic(1) Symbol Min Max Unit BDTxD Output Low Voltage (IBDTxD = 1.6 mA) VOLTX — 0.4 V BDTxD Output High Voltage (IBDTx = –800 μA) VOHTX VDD –0.8 — V 1. VDD = 5.0 Vdc + 10%, VSS = 0 Vdc, TA = –40 oC to +125 oC, unless otherwise noted 28.1.
PAGE 378
Electrical Specifications 28.2 Mechanical Specifications 28.2.1 51-Pin Plastic Leaded Chip Carrier (PLCC) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 379
Mechanical Specifications 28.2.2 64-Pin Quad Flat Pack (QFP) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 380
Electrical Specifications MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 381
Appendix A MC68HC908AS60 and MC68HC908AZ60 A.1 Changes from the MC68HC908AS60 and MC68HC908AZ60 (non-A suffix devices) A.1.1 Specification Specifications for MC68HC908AS60A and MC68HC908AZ60A devices have been integrated, reflecting the many commonalties. A.1.2 FLASH A.1.2.1 FLASH Architecture FLASH-1 and FLASH-2 are made from a new nonvolatile memory (NVM) technology. The architecture is now arranged in pages of 128 bytes and 2 rows per page.
PAGE 382
MC68HC908AS60 and MC68HC908AZ60 A.1.2.5 FLASH Block Protection The FLASH block protect registers are now 8-bit registers in place of 4-bit protecting array ranges that can be incremented by as little as 1 page (128 bytes) at a time as opposed to 8 Kbytes at a time on previous MCUs. Users making use of the block protect feature must change their block protect register.
PAGE 383
Changes from the MC68HC908AS60 and MC68HC908AZ60 (non-A suffix devices) A.1.4 CONFIG-2 CONFIG-2 register $FE09 has 2 new bits activated. Bit 3 is now a silicon hard set bit, which identifies this new A-suffix silicon (1) from the previous non-A suffix silicon (0). Bit 7 is now an EEPROM time base divider clock select bit selecting the reference clock source for the EEPROM time base divider module (refer to EEPROM changes described above). A.1.
PAGE 384
MC68HC908AS60 and MC68HC908AZ60 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 385
Appendix B MC68HC908AZ60E B.1 Introduction The MC68HC908AZ60E is a reduced EMC version of the MC68HC908AZ60A. Every care has been taken to insure compatibility with the MC68HC908AZ60A. Some additional features are available, however the default state of all affected modules match the MC68HC908AZ60A functionality. The reset state of all MC68HC908AZ60E registers match the MC68HC908AZ60A except for some reserved memory locations.
PAGE 386
MC68HC908AZ60E Table B-1.
PAGE 387
Detailed Memory Map Changes (MC68HC908AS60A references have been removed) Table B-1. External Pins Summary (Sheet 3 of 3) Function Driver Type Hysteresis(1) Reset State IRQ External Interrupt Request N/A Yes Input Hi-Z RST External Reset Open Drain Yes Output Low CANRx CAN Serial Input N/A Yes Input Hi-Z CANTx CAN Serial Output Output No Output Hi-Z Pin Name 1. Hysteresis is not 100% tested but is typically a minimum of 300 mV. B.
PAGE 388
MC68HC908AZ60E $0A00 RAM-2 1024 BYTES ↓ $0DFF $0E00 FLASH-2 29,184 BYTES ↓ $7FFF $8000 FLASH-1 32,256 BYTES ↓ $FDFF $FE00 SIM BREAK STATUS REGISTER (SBSR) $FE01 SIM RESET STATUS REGISTER (SRSR) $FE02 RESERVED $FE03 SIM BREAK FLAG CONTROL REGISTER (SBFCR) $FE04 RESERVED $FE05 RESERVED $FE06 RESERVED $FE07 RESERVED $FE08 FLASH-2 CONTROL REGISTER (FL2CR) $FE09 CONFIGURATION WRITE-ONCE REGISTER (CONFIG-2) $FE0A RESERVED $FE0B CONFIGURATION WRITE-ONCE REGISTER (CONFIG-3) $FE0C BREAK
PAGE 389
Detailed Memory Map Changes (MC68HC908AS60A references have been removed) $FE20 MONITOR ROM 256BYTES ↓ $FF1F $FF20 ↓ $FF6F UNIMPLEMENTED 80 BYTES $FF70 EEPROM-2 EEDIVH NONVOLATILE REGISTER (EE2DIVHNVR) $FF71 EEPROM-2 EEDIVL NONVOLATILE REGISTER (EE2DIVLNVR) $FF72 RESERVED $FF73 RESERVED $FF74 RESERVED $FF75 RESERVED $FF76 RESERVED $FF77 RESERVED $FF78 RESERVED $FF79 RESERVED $FF7A EEPROM-2 EE DIVIDER HIGH REGISTER (EE2DIVH) $FF7B EEPROM-2 EE DIVIDER LOW REGISTER (EE2DIVL) $FF7C
PAGE 390
MC68HC908AZ60E B.3 I/O Section Addresses $0000–$004F, shown in Figure B-2, contain the I/O Data, Status, and Control Registers. Differences from the MC68HC908AZ60A are shown in bold text. Addr.
PAGE 391
I/O Section Addr.
PAGE 392
MC68HC908AZ60E Addr.
PAGE 393
I/O Section Addr.
PAGE 394
MC68HC908AZ60E B.4 Additional Status and Control Registers Selected addresses in the range $FE00 to $FF88 contain additional Status and Control registers as shown in Figure B-3. A noted exception is the COP Control Register (COPCTL) at address $FFFF. Differences from the MC68HC908AZ60A are shown in bold text. Addr.
PAGE 395
Additional Status and Control Registers Addr.
PAGE 396
MC68HC908AZ60E B.5 Vector Addresses and Priority Addresses in the range $FFCC to $FFFF contain the user-specified vector locations. The vector addresses are shown in Table B-2.
PAGE 397
Ordering Information Vector Highest Priority Address MC68HC908AZ60E $FFEE TIMA CH3 Vector (High) $FFEF TIMA CH3 Vector (Low) $FFF0 TIMA CH2 Vector (High) $FFF1 TIMA CH2 Vector (Low) $FFF2 TIMA CH1 Vector (High) $FFF3 TIMA CH1 Vector (Low) $FFF4 TIMA CH0 Vector (High) $FFF5 TIMA CH0 Vector (Low) $FFF6 PIT Vector (High) $FFF7 PIT Vector (Low) $FFF8 PLL Vector (High) $FFF9 PLL Vector (Low) $FFFA IRQ1 Vector (High) $FFFB IRQ1 Vector (Low) $FFFC SWI Vector (High) $FFFD SWI Vect
PAGE 398
MC68HC908AZ60E B.7 Configuration Register (CONFIG-3) This section describes the configuration register (CONFIG-3). This register is unused on the MC68HC908AZ60A. This register contains one bit that configures the following option: Disables slew rate control for the SPI pins The configuration register is a write-once register. Once the register is written, further writes will have no effect until a reset occurs.
PAGE 399
ADC B.10 ADC This section explains the difference in functionality of the conversion complete bit (COCO) in the ADC10 status and control register (ADCSC). Writing ADCSC aborts the current conversion and initiates a new conversion (if the ADCH[4:0] bits are equal to a value other than all 1s). Bit 7 Read: COCO Write: Reset: 0 6 5 4 3 2 1 Bit 0 AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 1 1 1 1 1 = Unimplemented Figure B-5.
PAGE 400
MC68HC908AZ60E MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 401
Revision History Major Change Between Revision 5.0 and Revision 6.0 The following table lists the major change between the current revision of the MC68HC908AZ60A Technical Data Book, Rev 6.0, and the previous revision, Rev 5.0. Section affected Appendix B. MC68HC908AZ60E Description of change Added chapter describing the MC68HC908AZ60E. Major Changes Between Revision 5.0 and Revision 4.
PAGE 402
Revision History Major Changes Between Revision 2.0 and Revision 1.0 The following table lists the major changes between the current revision of the MC68HC908AZ60A Technical Data Book, Rev 2.0, and the previous revision, Rev 1.0. Section affected Description of change Timer Interface Module B (TIMB) Programmable Interrupt Timer (PIT) Various changes for clarification. Timer Interface Module A (TIMA) Major Changes Between Revision 1.0 and Revision 0.
PAGE 403
Revision History Section affected Monitor ROM (MON) Computer Operating Properly (COP) Description of change Modified Figure 1-Monitor Mode Circuit based upon recommendations from applications engineering. Correct text of Note 1 to Table 2-Mode Differences. Corrected type errors. Corrected text describing state of unprogrammed FLASH in Security subsection. Corrected Figure 6-Monitor Mode Entry Timing. Corrected state of COPL bit in Functional Description subsection.
PAGE 404
Revision History MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev.
PAGE 405
Glossary A — See “accumulator (A).” accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the accumulator to hold operands and results of arithmetic and logic operations. acquisition mode — A mode of PLL operation during startup before the PLL locks on a frequency. Also see "tracking mode." address bus — The set of wires that the CPU or DMA uses to read and write memory locations. addressing mode — The way that the CPU determines the operand address for an instruction.
PAGE 406
Glossary bus clock — The bus clock is derived from the CGMOUT output from the CGM. The bus clock frequency, fop, is equal to the frequency of the oscillator output, CGMXCLK, divided by four. byte — A set of eight bits. C — The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow.
PAGE 407
Glossary CPU registers — Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map. The CPU always has direct access to the information in these registers.
PAGE 408
Glossary high byte — The most significant eight bits of a word. illegal address — An address not within the memory map illegal opcode — A nonexistent opcode. I — The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts are disabled. index register (H:X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The lower byte is called X. In the indexed addressing modes, the CPU uses the contents of H:X to determine the effective address of the operand.
PAGE 409
Glossary mask option register (MOR) — An EPROM location containing bits that enable or disable certain MCU features. MCU — Microcontroller unit. See “microcontroller.” memory location — Each M68HC08 memory location holds one byte of data and has a unique address. To store information in a memory location, the CPU places the address of the location on the address bus, the data information on the data bus, and asserts the write signal.
PAGE 410
Glossary parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted. In a system that uses odd parity, every byte is expected to have an odd number of logic 1s. In an even parity system, every byte should have an even number of logic 1s. In the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts the number of logic 1s in each byte.
PAGE 411
Glossary reserved memory location — A memory location that is used only in special factory test modes. Writing to a reserved location has no effect. Reading a reserved location returns an unpredictable value. reset — To force a device to a known condition. ROM — Read-only memory. A type of memory that can be read but cannot be changed (written). The contents of ROM must be specified before manufacturing the MCU. SCI — See "serial communication interface module (SCI).
PAGE 412
Glossary toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a frequency. Also see "acquisition mode." two’s complement — A means of performing binary subtraction using addition techniques. The most significant bit of a two’s complement number indicates the sign of the number (1 indicates negative).
PAGE 413
PAGE 414
How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.