Datasheet

System Integration Module (SIM)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
112 Freescale Semiconductor
Figure 9-1. SIM Block Diagram
Register Name Bit 7654321Bit 0
SIM Break Status Register (SBSR) RRRRRRBWR
SIM Reset Status Register (SRSR) POR PIN COP ILOP ILAD 0 LVI 0
SIM Break Flag Control Register (SBFCR)BCFERRRRRRR
R
= Reserved
Figure 9-2. SIM I/O Register Summary
Table 9-1. I/O Register Address Summary
Register SBSR SRSR SBFCR
Address $FE00 $FE01 $FE03
STOP/WAIT
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERRUPT CONTROL
AND PRIORITY DECODE
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
MASTER
RESET
CONTROL
RESET
PIN LOGIC
LVI (FROM LVI MO D U LE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
RESET
CONTROL
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM CGM)
÷ 2