Datasheet

SIM Bus Clock Control and Generation
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 113
Table 9-2 shows the internal signal names used in this chapter.
9.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 9-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 10 Clock Generator Module
(CGM)).
Figure 9-3. CGM Clock Signals
9.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four. (See Chapter 10 Clock Generator Module (CGM)).
Table 9-2. Signal Name Conventions
Signal Name Description
CGMXCLK Buffered Version of OSC1 from Clock Generator Module (CGM)
CGMVCLK PLL Output
CGMOUT
PLL-Based or OSC1-Based Clock Output from CGM Module
(Bus Clock = CGMOUT Divided by Two)
IAB Internal Address Bus
IDB Internal Data Bus
PORRST Signal from the Power-On Reset Module to the SIM
IRST Internal Reset Signal
R/W
Read/Write Signal
PLL
OSC1
CGMXCLK
÷ 2
BUS CLOCK
GENERATORS
SIM
CGM
SIM COUNTER
PTC3
MONITOR MODE
CLOCK
SELECT
CIRCUIT
CGMVCLK
BCS
÷ 2
A
B
S*
CGMOUT
*When S = 1,
CGMOUT = B
USER MODE