Datasheet

Functional Description
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 129
10.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal enables the crystal oscillator
circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of
CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related
external components.
An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the
external clock to the OSC1 pin and let the OSC2 pin float.
10.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
Register Name Bit 7654321Bit 0
PLL Control Register (PCTL)
Read:
PLLIE
PLLF
PLLON BCS
1111
Write:
Reset:00101111
PLL Bandwidth Control Register (PB-
WC)
Read:
AUTO
LOCK
ACQ
XLD
0000
Write:
Reset:00000000
PLL Programming Register (PPG)
Read:
MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
Write:
Reset:01100110
= Unimplemented
Figure 10-2. I/O Register Summary
Table 10-1. I/O Register Address Summary
Register PCTL PBWC PPG
Address $001C $001D $001E