Datasheet

Clock Generator Module (CGM)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
134 Freescale Semiconductor
factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base
clock.
10.3.4 CGM External Connections
In its typical configuration, the CGM requires seven external components. Five of these are for the crystal
oscillator and two are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 10-3.
Figure 10-3 shows only the logical representation of the internal components and may not represent
actual circuitry. The oscillator configuration uses five components:
•Crystal, X
1
• Fixed capacitor, C
1
• Tuning capacitor, C
2
(can also be a fixed capacitor)
• Feedback resistor, R
B
• Series resistor, R
S
(optional)
The series resistor (R
S
) may not be required for all ranges of operation, especially with high-frequency
crystals. Refer to the crystal manufacturer’s data for more information.
Figure 10-3 also shows the external components for the PLL:
• Bypass capacitor, C
BYP
• Filter capacitor, C
F
Routing should be done with great care to minimize signal cross talk and noise. (See 10.9
Acquisition/Lock Time Specifications for routing information and more information on the filter capacitor’s
value and its effects on PLL performance).
Figure 10-3. CGM External Connections
C
1
C
2
C
F
SIMOSCEN
CGMXCLK
R
B
X
1
R
S
*
C
BYP
*R
S
can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data.
OSC1 OSC2
V
SS
CGMXFC
V
DD
V
DDA