Datasheet

Clock Generator Module (CGM)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
138 Freescale Semiconductor
In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is
stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
XLD — Crystal Loss Detect Bit
When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit can indicate whether the
crystal reference frequency is active or not.
1 = Crystal reference not active
0 = Crystal reference active
To check the status of the crystal reference, do the following:
1. Write a 1 to XLD.
2. Wait N × 4 cycles. N is the VCO frequency multiplier.
3. Read XLD.
The crystal loss detect function works only when the BCS bit is set, selecting CGMVCLK to drive
CGMOUT. When BCS is clear, XLD always reads as logic 0.
Bits 3–0 — Reserved for Test
These bits enable test functions not available in user mode. To ensure software portability from
development systems to user applications, software should write 0s to bits 3–0 when writing to PBWC.
10.5.3 PLL Programming Register
The PLL programming register contains the programming information for the modulo feedback divider
and the programming information for the hardware configuration of the VCO.
MUL7–MUL4 — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier,
N. (See 10.3.2.1 Circuits and 10.3.2.4 Programming the PLL). A value of $0 in the multiplier select bits
configures the modulo feedback divider the same as a value of $1. Reset initializes these bits to $6 to
give a default multiply value of 6.
Address: $001E
Bit 7654321Bit 0
Read:
MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
Write:
Reset:01100110
Figure 10-6. PLL Programming Register (PPG)