Datasheet

Acquisition/Lock Time Specifications
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 143
In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the
reference frequency. (See 10.3.2.3 Manual and Automatic PLL Bandwidth Modes). A certain number of
clock cycles, n
ACQ
, is required to ascertain that the PLL is within the tracking mode entry tolerance, Δ
TRK
,
before exiting acquisition mode. A certain number of clock cycles, n
TRK
, is required to ascertain that the
PLL is within the lock mode entry tolerance, Δ
Lock
. Therefore, the acquisition time, t
ACQ
, is an integer
multiple of n
ACQ
/f
CGMRDV
, and the acquisition to lock time, t
AL
, is an integer multiple of n
TRK
/f
CGMRDV
.
Also, since the average frequency over the entire measurement period must be within the specified
tolerance, the total time usually is longer than t
Lock
as calculated above.
In manual mode, it is usually necessary to wait considerably longer than t
Lock
before selecting the PLL
clock (see 10.3.3 Base Clock Selector Circuit), because the factors described in 10.9.2 Parametric
Influences on Reaction Time, may slow the lock time considerably.
When defining a limit in software for the maximum lock time, the value must allow for variation due to all
of the factors mentioned in this chapter, especially due to the C
F
capacitor and application specific
influences.
The calculated lock time is only an indication and it is the customer’s responsibility to allow enough of a
guard band for their application. Prior to finalizing any software and while determining the maximum lock
time, take into account all device to device differences. Typically, applications set the maximum lock time
as an order of magnitude higher than the measured value. This is considered sufficient for all such device
to device variation.
Freescale recommends measuring the lock time of the application system by utilizing dedicated software,
running in FLASH, EEPROM or RAM. This should toggle a port pin when the PLL is first configured and
switched on, then again when it goes from acquisition to lock mode and finally again when the PLL lock
bit is set. The resultant waveform can be captured on an oscilloscope and used to determine the typical
lock time for the microcontroller and the associated external application circuit.
For example,
NOTE
The filter capacitor should be fully discharged prior to making any
measurements.
t
LOCK
t
ACQ
t
AL
t
TRK
Complete and Lock Set
Init. low
Signal on port pin
t
ACQ
Complete
PLL Configured and switched on