Datasheet

MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 145
Chapter 11
Configuration Register (CONFIG-1)
11.1 Introduction
This chapter describes the configuration register (CONFIG-1), which contains bits that configure these
options:
• Resets caused by the LVI module
• Power to the LVI module
• LVI enabled during stop mode
• Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles)
• Computer operating properly module (COP)
• Stop instruction enable/disable.
11.2 Functional Description
The configuration register is a write-once register. Out of reset, the configuration register will read the
default value. Once the register is written, further writes will have no effect until a reset occurs.
NOTE
If the LVI module and the LVI reset signal are enabled, a reset occurs when
V
DD
falls to a voltage, LVI
TRIPF
, and remains at or below that level for at
least nine consecutive CPU cycles. Once an LVI reset occurs, the MCU
remains in reset until V
DD
rises to a voltage, LVI
TRIPR
.
LVISTOP — LVI Stop Mode Enable Bit
LVISTOP enables the LVI module in stop mode. (See Chapter 16 Low-Voltage Inhibit (LVI)).
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
NOTE
To have the LVI enabled in stop mode, the LVIPWR must be at a logic 1
and the LVISTOP bit must be at a logic 1. Take note that by enabling the
LVI in stop mode, the stop I
DD
current will be higher.
Address: $001F
Bit 7654321Bit 0
Read:
LVISTOP R LVIRST LVIPWR SSREC COPL STOP COPD
Write:
Reset:01110000
R=Reserved
Figure 11-1. Configuration Register (CONFIG-1)