Datasheet

COP Control Register
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 165
15.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
15.3.7 COPD
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. (See
Chapter 11 Configuration Register (CONFIG-1)).
15.3.8 COPL
The COPL signal reflects the state of the COP rate select bit. (COPL) in the configuration register. (See
Chapter 11 Configuration Register (CONFIG-1)).
15.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
15.5 Interrupts
The COP does not generate CPU interrupt requests.
15.6 Monitor Mode
The COP is disabled in monitor mode when V
Hi
is present on the IRQ pin or on the RST pin.
15.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
15.7.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the
COP counter in a CPU interrupt routine.
Address: $FFFF
Bit 7654321Bit 0
Read: Low Byte of Reset Vector
Write: Clear COP Counter
Reset: Unaffected by Reset
Figure 15-2. COP Control Register (COPCTL)