Datasheet

LVI Status Register
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 169
16.4 LVI Status Register
The LVI status register flags V
DD
voltages below the LVI
TRIPF
level.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
DD
voltage falls below the LVI
TRIPF
voltage for 32 to 40
CGMXCLK cycles. (See Table 16-1). Reset clears the LVIOUT bit.
16.5 LVI Interrupts
The LVI module does not generate interrupt requests.
16.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
16.6.1 Wait Mode
With the LVIPWR bit in the configuration register programmed to 1, the LVI module is active after a WAIT
instruction.
With the LVIRST bit in the configuration register programmed to 1, the LVI module can generate a reset
and bring the MCU out of wait mode.
Address: $FE0F
Bit 7654321Bit 0
Read:LVIOUT0000000
Write:
Reset:00000000
= Unimplemented
Figure 16-3. LVI Status Register (LVISR)
Table 16-1. LVIOUT Bit Indication
V
DD
LVIOUT
At Level:
For Number of
CGMXCLK Cycles:
V
DD
> LVI
TRIPR
Any 0
V
DD
< LVI
TRIPF
< 32 CGMXCLK Cycles 0
V
DD
< LVI
TRIPF
Between 32 and 40
CGMXCLK Cycles
0 or 1
V
DD
< LVI
TRIPF
> 40 CGMXCLK Cycles 1
LVI
TRIPF
< V
DD
< LVI
TRIPR
Any Previous Value