Datasheet

External Interrupt Module (IRQ)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
172 Freescale Semiconductor
Figure 17-1. IRQ Block Diagram
The external interrupt pin is falling-edge triggered and is software- configurable to be both falling-edge
and low-level triggered. The MODE bit in the ISCR controls the triggering sensitivity of the IRQ
pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software
clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both
of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to a high level
The vector fetch or software clear may occur before or after the interrupt pin returns to a high level. As
long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1
control bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the ISCR masks all external interrupt requests. A latched interrupt request is
not presented to the interrupt priority logic unless the corresponding IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. (See Figure 17-3).
Addr. Register Name Bit 7654321Bit 0
$001A IRQ Status/Control Register (ISCR)
Read:0000IRQF0
IMASK MODE
Write:RRRRRACK
R
= Reserved
Figure 17-2. IRQ I/O Register Summary
ACK
IMASK
DQ
CK
CLR
IRQ
HIGH
INTERRUPT
TO MODE
SELECT
LOGIC
IRQ
LATCH
REQUEST
IRQ
V
DD
MODE
VOLTAGE
DETECT
SYNCHRO-
NIZER
IRQF
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
INTERNAL ADDRESS BUS