Datasheet

IRQ Status and Control Register
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 175
17.6 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR
has these functions:
• Shows the state of the IRQ interrupt flag
• Clears the IRQ interrupt latch
• Masks IRQ interrupt request
• Controls triggering sensitivity of the IRQ
interrupt pin
IRQF — IRQ
Flag Bit
This read-only status bit is high when the IRQ
interrupt is pending.
1 = IRQ
interrupt pending
0 = IRQ
interrupt not pending
ACK — IRQ
Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as logic 0. Reset clears
ACK.
IMASK — IRQ
Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ
interrupt requests. Reset clears IMASK.
1 = IRQ
interrupt requests disabled
0 = IRQ
interrupt requests enabled
MODE — IRQ
Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ
pin. Reset clears MODE.
1 = IRQ
interrupt requests on falling edges and low levels
0 = IRQ
interrupt requests on falling edges only
Address: $001A
Bit 7654321Bit 0
Read:0000IRQF0
IMASK MODE
Write:RRRR ACK
Reset:00000000
= Unimplemented R = Reserved
Figure 17-4. IRQ Status and Control Register (ISCR)