Datasheet

Serial Communications Interface (SCI)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
180 Freescale Semiconductor
18.4.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 18-3.
Figure 18-3. SCI Data Formats
18.4.2 Transmitter
Figure 18-4 shows the structure of the SCI transmitter.
18.4.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3)
is the ninth bit (bit 8).
18.4.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character out to the TxD pin. The SCI data
register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To
initiate an SCI transmission:
1. Enable the SCI by writing a 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a 1 to the transmitter enable bit (TE) in SCI control register 2
(SCC2).
3. Clear the SCI transmitter empty bit (SCTE) by first reading SCI status register 1 (SCS1) and then
writing to the SCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit
shift register. A 0 start bit automatically goes into the least significant bit position of the transmit shift
register. A 1 stop bit goes into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data
bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a
transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, 1.
If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver
relinquish control of the port E pins.
BIT 5
START
BIT
BIT 0 BIT 1
NEXT
STOP
BIT
START
BIT
8-BIT DATA FORMAT
(BIT M IN SCC1 CLEAR)
START
BIT
BIT 0
NEXT
STOP
BIT
START
BIT
9-BIT DATA FORMAT
(BIT M IN SCC1 SET)
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
BIT 2 BIT 3 BIT 4 BIT 6 BIT 7
PARITY
OR DATA
BIT
PARITY
OR DATA
BIT