Datasheet

Serial Peripheral Interface (SPI)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
212 Freescale Semiconductor
delay will be no longer than a single SPI bit time. That is, the maximum delay between the write to SPDR
and the start of the SPI transmission is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32
MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
Figure 19-6. Transmission Start Delay (Master)
WRITE
TO SPDR
INITIATION DELAY
BUS
MOSI
SCK
CPHA = 1
SCK
CPHA = 0
SCK CYCLE
NUMBER
MSB BIT 6
12
CLOCK
WRITE
TO SPDR
EARLIEST
LATEST
SCK = INTERNAL CLOCK ÷ 2;
EARLIEST LATEST
2 POSSIBLE START POINTS
SCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
EARLIEST LATESTSCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
EARLIEST LATESTSCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
WRITE
TO SPDR
WRITE
TO SPDR
WRITE
TO SPDR
BUS
CLOCK
BIT 5
3
BUS
CLOCK
BUS
CLOCK
BUS
CLOCK
⎧ ⎨
⎩
⎮ ⎮ ⎮ ⎮ ⎮
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN