Datasheet

Error Conditions
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 213
19.6 Error Conditions
Two flags signal SPI error conditions:
1. Overflow (OVRF in SPSCR) — Failing to read the SPI data register before the next byte enters the
shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and
the unread byte still can be read by accessing the SPI data register. OVRF is in the SPI status and
control register.
2. Mode fault error (MODF in SPSCR) — The MODF bit indicates that the voltage on the slave select
pin (SS
) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
19.6.1 Overflow Error
The overflow flag (OVRF in SPSCR) becomes set if the SPI receive data register still has unread data
from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. (See Figure
19-4 and Figure 19-5.) If an overflow occurs, the data being received is not transferred to the receive data
register so that the unread data can still be read. Therefore, an overflow error always indicates the loss
of data.
OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE in SPSCR)
is also set. MODF and OVRF can generate a receiver/error CPU interrupt request. (See Figure 19-9). It
is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request.
However, leaving MODFEN low prevents MODF from being set.
If an end-of-block transmission interrupt was meant to pull the MCU out of wait, having an overflow
condition without overflow interrupts enabled causes the MCU to hang in wait mode. If the OVRF is
enabled to generate an interrupt, it can pull the MCU out of wait mode instead.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition.
Figure 19-7 shows how it is possible to miss an overflow.
Figure 19-7. Missed Read of Overflow Condition
READ SPDR
READ SPSCR
OVRF
SPRF
BYTE 1 BYTE 2 BYTE 3 BYTE 4
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
CPU READS BYTE 1 IN SPDR,
BYTE 2 SETS SPRF BIT.
CPU READS SPSCRW WITH SPRF BIT SET
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
1
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
CLEARING SPRF BIT.
BUT NOT OVRF BIT.
OVRF BIT IS SET. BYTE 4 IS LOST.
AND OVRF BIT CLEAR.
AND OVRF BIT CLEAR.