Datasheet

I/O Registers
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 221
19.12.5 V
SS
(Clock Ground)
V
SS
is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. To
reduce the ground return path loop and minimize radio frequency (RF) emissions, connect the ground pin
of the slave to the V
SS
pin.
19.13 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR $0010)
• SPI status and control register (SPSCR $0011)
• SPI data register (SPDR $0012)
19.13.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Selects CPU interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure
19-4 and Figure 19-5.) To transmit data between SPI modules, the SPI modules must have identical
CPOL bits. Reset clears the CPOL bit.
Address: $0010
Bit 7654321Bit 0
Read:
SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE
Write:
Reset:00101000
R= Reserved
Figure 19-12. SPI Control Register (SPCR)