Datasheet

I/O Registers
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 237
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD4/ATD12/TBCLK pin or one of the seven prescaler outputs
as the input to the TIMB counter as Table 20-1 shows. Reset clears the PS[2:0] bits.
20.8.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes of the value in the TIMB counter.
Reading the high byte (TBCNTH) latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL is read. Reset clears the TIMB
counter registers. Setting the TIMB reset bit (TRST) also clears the TIMB counter registers.
NOTE
If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL by
reading TBCNTL before exiting the break interrupt. Otherwise, TBCNTL
retains the value latched during the break.
Table 20-1. Prescaler Selection
PS[2:0] TIMB Clock Source
000 Internal Bus Clock ÷1
001 Internal Bus Clock ÷ 2
010 Internal Bus Clock ÷ 4
011 Internal Bus Clock ÷ 8
100 Internal Bus Clock ÷ 16
101 Internal Bus Clock ÷ 32
110 Internal Bus Clock ÷ 64
111 PTD4/ATD12/TBCLK
Register Name and Address TBCNTH — $0041
Bit 7654321Bit 0
Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
Write:
Reset:00000000
Register Name and Address TBCNTL — $0042
Bit 7654321Bit 0
Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Write:
Reset:00000000
= Unimplemented
Figure 20-5. TIMB Counter Registers (TBCNTH and TBCNTL)