Datasheet

Programmable Interrupt Timer (PIT)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
244 Freescale Semiconductor
21.4 PIT Counter Prescaler
The clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates
from the internal bus clock. The prescaler select bits, PPS[2:0], in the status and control register select
the PIT clock source.
The value in the PIT counter modulo registers and the selected prescaler output determines the frequency
of the periodic interrupt. The PIT overflow flag (POF) is set when the PIT counter value reaches the
modulo value programmed in the PIT counter modulo registers. The PIT interrupt enable bit, POIE,
enables PIT overflow CPU interrupt requests. POF and POIE are in the PIT status and control register.
21.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
21.5.1 Wait Mode
The PIT remains active after the execution of a WAIT instruction. In wait mode the PIT registers are not
accessible by the CPU. Any enabled CPU interrupt request from the PIT can bring the MCU out of wait
mode.
Register Name Bit 7654321Bit 0
PIT Status and Control Register (PSC)
Read: POF
POIE PSTOP
00
PPS2 PPS1 PPS0
Write: 0 PRST
Reset:00100000
PIT Counter Register High (PCNTH)
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
PIT Counter Register Low (PCNTL)
Read:Bit 7654321Bit 0
Write:
Reset:00000000
PIT Counter Modulo Register High
(PMODH)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
PIT Counter Modulo Register Low
(PMODL)
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
=Unimplemented
Figure 21-2. PIT I/O Register Summary
Table 21-1. PIT I/O Register Address Summary
Register PSC PCNTH PCNTL PMODH PMODL
Address $004B $004C $004D $004E $004F