Datasheet

I/O Registers
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 247
21.7.2 PIT Counter Registers
The two read-only PIT counter registers contain the high and low bytes of the value in the PIT counter.
Reading the high byte (PCNTH) latches the contents of the low byte (PCNTL) into a buffer. Subsequent
reads of PCNTH do not affect the latched PCNTL value until PCNTL is read. Reset clears the PIT counter
registers. Setting the PIT reset bit (PRST) also clears the PIT counter registers.
NOTE
If you read PCNTH during a break interrupt, be sure to unlatch PCNTL by
reading PCNTL before exiting the break interrupt. Otherwise, PCNTL
retains the value latched during the break.
Table 21-2. Prescaler Selection
PPS[2:0] PIT Clock Source
000 Internal Bus Clock ÷1
001 Internal Bus Clock ÷ 2
010 Internal Bus Clock ÷ 4
011 Internal Bus Clock ÷ 8
100 Internal Bus Clock ÷ 16
101 Internal Bus Clock ÷ 32
110 Internal Bus Clock ÷ 64
111 Internal Bus Clock ÷ 64
Address: $004C
Bit 7654321Bit 0
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Address: $004D
Bit 7654321Bit 0
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
= Unimplemented
Figure 21-4. PIT Counter Registers (PCNTH–PCNTL)