Datasheet

Port C
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 255
DDRC[5:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins
as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 22-10 shows the port C I/O logic.
Figure 22-10. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a
logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-3 summarizes the operation of the port C pins.
Table 22-3. Port C Pin Functions
Bit
Value
PTC
Bit
I/O Pin
Mode
Accesses to DDRC Accesses to PTC
Read/Write Read Write
0 2 Input, Hi-Z DDRC[2] Pin PTC2
1 2 Output DDRC[2] 0 —
0 X Input, Hi-Z DDRC[5:0] Pin
PTC[5:0]
(1)
1 X Output DDRC[5:0] PTC[5:0] PTC[5:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
READ DDRC ($0006)
WRITE DDRC ($0006)
RESET
WRITE PTC ($0002)
READ PTC ($0002)
PTCx
DDRCx
PTCx
INTERNAL DATA BUS