Datasheet

Port F
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 261
22.7.1 Port F Data Register
The port F data register contains a data latch for each of the seven port F pins.
PTF[6:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of each port F pin is under the control
of the corresponding bit in data direction register F. Reset has no effect on PTF[6:0].
TACH[5:2] — Timer A Channel I/O Bits
The PTF3–PTF0/TACH2 pins are the TIM input capture/output compare pins. The edge/level select
bits, ELSxB:ELSxA, determine whether the PTF3–PTF0/TACH2 pins are timer channel I/O pins or
general-purpose I/O pins. (See 25.8.1 TIMA Status and Control Register).
TBCH[1:0] — Timer B Channel I/O Bits
The PTF5/TBCH1–PTF4/TBCH0 pins are the TIMB input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTF5/TBCH1–PTF4/TBCH0 pins are timer channel
I/O pins or general-purpose I/O pins. (See 20.8.1 TIMB Status and Control Register).
NOTE
Data direction register F (DDRF) does not affect the data direction of port F
pins that are being used by the TIM. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. (See Table 22-6).
22.7.2 Data Direction Register F
Data direction register F determines whether each port F pin is an input or an output. Writing a logic 1 to
a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the output buffer.
Address: $0009
Bit 7654321Bit 0
Read: 0
PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0
Write: R
Reset: Unaffected by Reset
Alternative
Function:
TBCH1 TBCH0 TACH5 TACH4 TACH3 TACH2
R= Reserved
Figure 22-17. Port F Data Register (PTF)
Address: $000D
Bit 7654321Bit 0
Read: 0
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
Write: R
Reset:00000000
R= Reserved
Figure 22-18. Data Direction Register F (DDRF)