Datasheet

Input/Output Ports
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
262 Freescale Semiconductor
DDRF[6:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears DDRF[6:0], configuring all port F pins
as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 22-19 shows the port F I/O logic.
Figure 22-19. Port F I/O Circuit
When bit DDRFx is a logic 1, reading address $0009 reads the PTFx data latch. When bit DDRFx is a
logic 0, reading address $0009 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-6 summarizes the operation of the port F pins.
Table 22-6. Port F Pin Functions
DDRF
Bit
PTF
Bit
I/O Pin
Mode
Accesses to DDRF Accesses to PTF
Read/Write Read Write
0 X Input, Hi-Z DDRF[6:0] Pin
PTF[6:0]
(1)
1 X Output DDRF[6:0] PTF[6:0] PTF[6:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
READ DDRF ($000D)
WRITE DDRF ($000D)
RESET
WRITE PTF ($0009)
READ PTF ($0009)
PTFx
DDRFx
PTFx
INTERNAL DATA BUS