Datasheet
MSCAN Controller (MSCAN08)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
282 Freescale Semiconductor
23.12 Programmer’s Model of Message Storage
This subsection details the organization of the receive and transmit message buffers and the associated
control registers. For reasons of programmer interface simplification, the receive and transmit message
buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a
13-byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit
buffers.
23.12.1 Message Buffer Outline
Figure 23-11 shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 23-12. All bits of
the 13-byte data structure are undefined out of reset.
NOTE
The foreground receive buffer can be read anytime but cannot be written.
The transmit buffers can be read or written anytime.
23.12.2 Identifier Registers
The identifiers consist of either 11 bits (ID10–ID0) for the standard, or 29 bits (ID28–ID0) for the extended
format. ID10/28 is the most significant bit and is transmitted first on the bus during the arbitration
procedure. The priority of an identifier is defined to be highest for the smallest binary number.
SRR — Substitute Remote Request
This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission
buffers and will be stored as received on the CAN bus for receive buffers.
Addr Register Name
$05x0 IDENTIFIER REGISTER 0
$05x1 IDENTIFIER REGISTER 1
$05x2 IDENTIFIER REGISTER 2
$05x3 IDENTIFIER REGISTER 3
$05x4 DATA SEGMENT REGISTER 0
$05x5 DATA SEGMENT REGISTER 1
$05x6 DATA SEGMENT REGISTER 2
$05x7 DATA SEGMENT REGISTER 3
$05x8 DATA SEGMENT REGISTER 4
$05x9 DATA SEGMENT REGISTER 5
$05xA DATA SEGMENT REGISTER 6
$05xB DATA SEGMENT REGISTER 7
$05xC DATA LENGTH REGISTER
$05xD
TRANSMIT BUFFER PRIORITY REGISTER
(1)
$05xE UNUSED
$05xF UNUSED
1. Where x equals the following:
x = 4 for receiver buffer
x = 5 for transmit buffer 1
x = 6 for transmit buffer 2
x = 7 for transmit buffer 3
2. Not applicable for receive buffers
Figure 23-10. Message Buffer Organization