Datasheet

Programmer’s Model of Control Registers
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 289
23.13.3 MSCAN08 Bus Timing Register 0
SJW1 and SJW0 — Synchronization Jump Width
The synchronization jump width (SJW) defines the maximum number of time quanta (T
q
) clock cycles
by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on
the bus (see Table 23-6).
BRP5–BRP0 — Baud Rate Prescaler
These bits determine the time quanta (T
q
) clock, which is used to build up the individual bit timing,
according to Table 23-7.
NOTE
The CBTR0 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
Address: $0502
Bit 7654321Bit 0
Read:
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Write:
Reset:00000000
Figure 23-17. Bus Timing Register 0 (CBTR0)
Table 23-6. Synchronization Jump Width
SJW1 SJW0 Synchronization Jump Width
00
1 T
q
cycle
01
2 T
q
cycle
10
3 T
q
cycle
11
4 T
q
cycle
Table 23-7. Baud Rate Prescaler
BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler Value (P)
000000 1
000001 2
000010 3
000011 4
:::::: :
:::::: :
111111 64