Datasheet

MSCAN Controller (MSCAN08)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
298 Freescale Semiconductor
23.13.12 MSCAN08 Identifier Acceptance Registers
On reception each message is written into the background receive buffer. The CPU is only signalled to
read the message, however, if it passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message will be overwritten by the next message (dropped).
The acceptance registers of the MSCAN08 are applied on the IDR0 to IDR3 registers of incoming
messages in a bit by bit manner.
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers only
the first two (CIDMR0/1 and CIDAR0/1) are applied.
AC7–AC0 — Acceptance Code Bits
AC7–AC0 comprise a user-defined sequence of bits with which the corresponding bits of the related
identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is
then masked with the corresponding identifier mask register.
NOTE
The CIDAR0–3 registers can be written only if the SFTRES bit in CMCR0
is set
CIDAR0 Address: $0510
Bit 7654321Bit 0
Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write:
Reset: Unaffected by Reset
CIDAR1 Address: $050511
Bit 7654321Bit 0
Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write:
Reset: Unaffected by Reset
CIDAR2 Address: $0512
Bit 7654321Bit 0
Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write:
Reset: Unaffected by Reset
CIDAR3 Address: $0513
Bit 7654321Bit 0
Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write:
Reset: Unaffected by Reset
Figure 23-26. Identifier Acceptance Registers (CIDAR0–CIDAR3)