Datasheet

Timer Interface Module A (TIMA)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
320 Freescale Semiconductor
25.8.4 TIMA Channel Status and Control Registers
Each of the TIMA channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare or PWM operation
• Selects high, low or toggling output on output compare
• Selects rising edge, falling edge or any edge as the active input capture trigger
• Selects output toggling on TIMA overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Register Name and Address TASC0 — $0026
Bit 7654321Bit 0
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
Register Name and Address TASC1 — $0029
Bit 7654321Bit 0
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0 R
Reset:00000000
R= Reserved
Register Name and Address TASC2 — $002C
Bit 7654321Bit 0
Read: CH2F
CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX
Write: 0
Reset:00000000
Register Name and Address TASC3 — $002F
Bit 7654321Bit 0
Read: CH3F
CH3IE
0
MS3A ELS3B ELS3A TOV3 CH3MAX
Write: 0 R
Reset:00000000
Register Name and Address TASC4 — $0032
Bit 7654321Bit 0
Read: CH4F
CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX
Write: 0
Reset:00000000
Figure 25-7. TIMA Channel Status and Control Registers (TASC0–TASC5)