Datasheet

Timer Interface Module A (TIMA)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
322 Freescale Semiconductor
When ELSxB:A = 00, this read/write bit selects the initial output level of the TACHx pin once PWM,
output compare mode or input capture mode is enabled. See Table 25-2. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIMA status and control register (TASC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port E or port F and pin
PTEx/TACHx or pin PTFx/TACHx is available as a general-purpose I/O pin. However, channel x is at
a state determined by these bits and becomes transparent to the respective pin when PWM, input
capture mode or output compare operation mode is enabled. Table 25-2 shows how ELSxB and
ELSxA work. Reset clears the ELSxB and ELSxA bits.
NOTE
Before enabling a TIMA channel register for input capture operation, make
sure that the PTEx/TACHx pin or PTFx/TACHx pin is stable for at least two
bus clocks.
Table 25-2. Mode, Edge, and Level Selection
MSxB MSxA ELSxB ELSxA Mode Configuration
X0 0 0
Output preset
Pin under port control; initial output level high
X 1 0 0 Pin under port control; initial output level low
00 0 1
Input capture
Capture on rising edge only
0 0 1 0 Capture on falling edge only
0 0 1 1 Capture on rising or falling edge
01 0 0
Output compare
or PWM
Software compare only
0 1 0 1 Toggle output on compare
0 1 1 0 Clear output on compare
0 1 1 1 Set output on compare
1X 0 1
Buffered output
compare or
buffered PWM
Toggle output on compare
1 X 1 0 Clear output on compare
1 X 1 1 Set output on compare