Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
328 Freescale Semiconductor
Figure 26-1. ADC Block Diagram
26.3.1 ADC Port I/O Pins
PTD6/ATD14/TACLK–PTD0/ATD8 and PTB7/ATD7–PTB0/ATD0 are general-purpose I/O pins that
share with the ADC channels.
The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC
overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins
are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or
DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in
use by the ADC will return a 0 if the corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the
value in the port data latch is read.
NOTE
Do not use ADC channels ATD14 or ATD12 when using the
PTD6/ATD14/TACLK or PTD4/ATD12/TBCLK
pins as the clock inputs for
the 16-bit Timers.
INTERNAL
DATA BUS
READ DDRB/DDRB
WRITE DDRB/DDRD
RESET
WRITE PTB/PTD
READ PTB/PTD
PTBx/PTDx
DDRBx/DDRDx
PTBx/PTDx
INTERRUPT
LOGIC
CHANNEL
SELECT
ADC
CLOCK
GENERATOR
CONVERSION
COMPLETE
ADC VOLTAGE IN
ADCVIN
ADC CLOCK
CGMXCLK
BUS CLOCK
ADCH[4:0]
ADC DATA REGISTER
ADIV[2:0] ADICLK
AIEN
COCO
DISABLE
DISABLE
ADC CHANNEL x