Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
332 Freescale Semiconductor
26.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Table 26-1. Mux Channel Select
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select
00000 PTB0/ATD0
00001 PTB1/ATD1
00010 PTB2/ATD2
00011 PTB3/ATD3
00100 PTB4/ATD4
00101 PTB5/ATD5
00110 PTB6/ATD6
00111 PTB7/ATD7
01000 PTD0/ATD8/ATD8
01001 PTD1/ATD9/ATD9
01010PTD2/ATD10/ATD10
01011PTD3/ATD11/ATD11
0 1 1 0 0 PTD4/ATD12/TBCLK/ATD12
01101PTD5/ATD13/ATD13
0 1 1 1 0 PTD6/ATD14/TACLK/ATD14
Range 01111 ($0F) to 11010 ($1A)
Unused (see Note 1)
Unused (see Note 1)
11011 Reserved
1 1 1 0 0 Unused (see Note 1)
11101
V
REFH
(see Note 2)
11110
V
SSA
/V
REFL
(see Note 2)
11111 [ADC power off]
Notes:
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are used
to verify the operation of the ADC converter both in production test and for user applica-
tions.
Address: $0039
Bit 7654321Bit 0
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset: Indeterminate after Reset
= Unimplemented
Figure 26-3. ADC Data Register (ADR)