Datasheet

I/O Registers
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 333
26.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock. Table 26-2 shows the available clock configurations. The ADC clock should be
set to approximately 1 MHz.
ADICLK — ADC Input Clock Register Bit
ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC
clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be
guaranteed. See 28.1.6 ADC Characteristics.
1 = Internal bus clock
0 = External clock (CGMXCLK)
NOTE
During the conversion process, changing the ADC clock will result in an
incorrect conversion.
Address: $003A
Bit 7654321Bit 0
Read:
ADIV2 ADIV1 ADIV0 ADICLK
0000
Write:
Reset: 0 0000000
= Unimplemented
Figure 26-4. ADC Input Clock Register (ADICLK)
Table 26-2. ADC Clock Divide Ratio
ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 ADC Input Clock /1
0 0 1 ADC Input Clock / 2
0 1 0 ADC Input Clock / 4
0 1 1 ADC Input Clock / 8
1 X X ADC Input Clock / 16
X = don’t care
f
XCLK
or Bus Frequency
1 MHz = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
ADIV[2:0]