Datasheet

Byte Data Link Controller (BDLC)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
336 Freescale Semiconductor
Figure 27-1. BDLC Block Diagram
Addr. Name Bit 7 6 5 4 3 2 1 Bit 0
$003B
BDLC Analog and Rou5ndtrip
Delay Register (BARD)
Read:
ATE RXPOL
00
BO3 BO2 BO1 BO0
Write: R R
$003C
BDLC Control Register 1
(BCR1)
Read:
IMSG CLKS R1 R0
00
IE WCM
Write: R R
$003D
BDLC Control Register 2
(BCR2)
Read:
ALOOP DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0
Write:
$003E
BDLC State Vector Register
(BSVR)
Read: 0 0 I3 I2 I1 I0 0 0
Write:RRR R RRRR
$003F BDLC Data Register (BDR)
Read:
BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0
Write:
R
= Reserved
Figure 27-2. BDLC I/O Register Summary
CPU INTERFACE
TO J1850 BUS
MUX INTERFACE
PROTOCOL HANDLER
PHYSICAL INTERFACE
TO CPU
BDLC