Datasheet

BDLC MUX Interface
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 339
27.4 BDLC MUX Interface
The MUX interface is responsible for bit encoding/decoding and digital noise filtering between the protocol
handler and the physical interface.
Figure 27-4. BDLC Block Diagram
27.4.1 Rx Digital Filter
The receiver section of the BDLC includes a digital low pass filter to remove narrow noise pulses from the
incoming message. An outline of the digital filter is shown in Figure 27-5.
Figure 27-5. BDLC Rx Digital Filter Block Diagram
27.4.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see f
BDLC
parameter in Table 27-3).
At each positive edge of the clock signal, the current state of the receiver physical interface (BDRxD)
signal is sampled. The BDRxD signal state is used to determine whether the counter should increment or
decrement at the next negative edge of the clock signal.
CPU INTERFACE
TO J1850 BUS
MUX INTERFACE
PROTOCOL HANDLER
PHYSICAL INTERFACE
TO CPU
BDLC
4-BIT UP/DOWN COUTER
DATA
LATCH
UP/DOWN
OUT D Q
FILTERED
RX DATA OUT
MUX INTERFACE
INPUT
SYNC
DQ
RX DATA
FROM
PHYSICAL
INTERFACE
CLOCK
(BDRXD)