Datasheet

Byte Data Link Controller (BDLC)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
348 Freescale Semiconductor
Figure 27-10. J1850 VPW Received BREAK Symbol Times
27.4.5 Message Arbitration
Message arbitration on the J1850 bus is accomplished in a non-destructive manner, allowing the
message with the highest priority to be transmitted, while any transmitters which lose arbitration simply
stop transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that another message is in progress, it waits
until the bus is idle. However, if multiple nodes begin to transmit in the same synchronization window,
message arbitration will occur beginning with the first bit after the SOF symbol and will continue with each
bit thereafter.
The variable pulse width modulation (VPW) symbols and J1850 bus electrical characteristics are chosen
carefully so that a logic 0 (active or passive type) will always dominate over a logic 1 (active or passive
type) that is simultaneously transmitted. Hence, logic 0s are said to be dominant and logic 1s are said to
be recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted a recessive bit, the node loses
arbitration and immediately stops transmitting. This is known as bitwise arbitration.
Figure 27-11. J1850 VPW Bitwise Arbitrations
(2) VALID BREAK SYMBOL
240 μs
e
ACTIVE
PASSIVE
TRANSMITTER A
TRANSMITTER B
J1850 BUS
SOF
DATA
BIT 1
DATA
BIT 4
DATA
BIT 5
0
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
TRANSMITTER B WINS
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
0
0
1
1
1
DATA
BIT 2
1
1
1
DATA
BIT 3
0
0
0
0
1
ARBITRATION AND
CONTINUES
TRANSMITTING