Datasheet

BDLC CPU Interface
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 353
27.5.5.5 Summary
27.6 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the BDLC and consists of five user
registers.
• BDLC analog and roundtrip delay register (BARD)
• BDLC control register 1 (BCR1)
• BDLC control register 2 (BCR2)
• BDLC state vector register (BSVR)
• BDLC data register (BDR)
Figure 27-14. BDLC Block Diagram
Table 27-1. BDLC J1850 Bus Error Summary
Error Condition BDLC Function
Transmission Error
For invalid bits or framing symbols on non-byte
boundaries, invalid symbol interrupt will be
generated. BDLC stops transmission.
Cyclical Redundancy Check (CRC)
Error
CRC error interrupt will be generated. The BDLC will
wait for SOF.
Invalid Symbol: BDLC Receives
Invalid Bits (Noise)
The BDLC will abort transmission immediately.
Invalid symbol interrupt will be generated.
Framing Error
Invalid symbol interrupt will be generated. The BDLC
will wait for start-of-frame (SOF).
Bus Short to V
DD
The BDLC will not transmit until the bus is idle.
Bus Short to GND
Thermal overload will shut down physical interface.
Fault condition is reflected in BSVR as an invalid
symbol.
BDLC Receives BREAK Symbol.
The BDLC will wait for the next valid SOF. Invalid
symbol interrupt will be generated.
CPU INTERFACE
TO J1850 BUS
MUX INTERFACE
PROTOCOL HANDLER
PHYSICAL INTERFACE
TO CPU
BDLC