Datasheet

Byte Data Link Controller (BDLC)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
354 Freescale Semiconductor
27.6.1 BDLC Analog and Roundtrip Delay Register
This register programs the BDLC to compensate for various delays of different external transceivers. The
default delay value is16 μs. Timing adjustments from 9 μs to 24 μs in steps of 1 μs are available. The
BARD register can be written only once after each reset, after which they become read-only bits. The
register may be read at any time.
ATE — Analog Transceiver Enable Bit
The analog transceiver enable (ATE) bit is used to select either the on-board or an off-chip analog
transceiver.
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
NOTE
This device does not contain an on-board transceiver. This bit should be
programmed to a 0 for proper operation.
RXPOL — Receive Pin Polarity Bit
The receive pin polarity (RXPOL) bit is used to select the polarity of an incoming signal on the receive
pin. Some external analog transceivers invert the receive signal from the J1850 bus before feeding it
back to the digital receive pin.
1 = Select normal/true polarity; true non-inverted signal from the J1850 bus; for example, the
external transceiver does not invert the receive signal
0 = Select inverted polarity, where an external transceiver inverts the receive signal from the J1850
bus
B03–B00 — BARD Offset Bits
Table 27-2 shows the expected transceiver delay with respect to BARD offset values.
Address: $003B
Bit 7654321Bit 0
Read:
ATE RXPOL
00
BO3 BO2 BO1 BO0
Write: R R
Reset:11000111
R= Reserved
Figure 27-15. BDLC Analog and Roundtrip Delay Register (BARD)
Table 27-2. BDLC Transceiver Delay
BARD Offset Bits B0[3:0]
Corresponding Expected
Transceiver’s Delays (μs)
0000 9
0001 10
0010 11
0011 12
0100 13
0101 14
0110 15
0111 16