Datasheet

BDLC CPU Interface
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 361
27.6.4 BDLC State Vector Register
This register is provided to substantially decrease the CPU overhead associated with servicing interrupts
while under operation of a multiplex protocol. It provides an index offset that is directly related to the
BDLC’s current state, which can be used with a user-supplied jump table to rapidly enter an interrupt
service routine. This eliminates the need for the user to maintain a duplicate state machine in software.
I0, I1, I2, and I3 — Interrupt Source Bits
These bits indicate the source of the interrupt request that currently is pending. The encoding of these
bits are listed in Table 27-5.
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the BDLC data register needs
servicing (RDRF, RXIFR, or TDRE conditions). RXIFR and RDRF can be cleared only by a read of the
BSVR followed by a read of the BDLC data register (BDR). TDRE can either be cleared by a read of the
BSVR followed by a write to the BDLC BDR or by setting the TEOD bit in BCR2.
Address: $003E
Bit 7654321Bit 0
Read:0 0 I3I2I1I0 0 0
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 27-19. BDLC State Vector Register (BSVR)
Table 27-5. BDLC Interrupt Sources
BSVR I3 I2 I1 I0 Interrupt Source Priority
$00 0000 No Interrupts Pending 0 (Lowest)
$04 0001 Received EOF 1
$08 0010 Received IFR Byte (RXIFR) 2
$0C 0011 BDLC Rx Data Register Full (RDRF) 3
$10 0100 BDLC Tx Data Register Empty (TDRE) 4
$14 0101 Loss of Arbitration 5
$18 0110 Cyclical Redundancy Check (CRC) Error 6
$1C 0111 Symbol Invalid or Out of Range 7
$20 1000 Wakeup 8 (Highest)