Datasheet

Byte Data Link Controller (BDLC)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
364 Freescale Semiconductor
If this mode is entered while the BDLC is receiving a message, the first subsequent received edge will
cause the BDLC to wake up immediately, generate a CPU interrupt request, and wait for the BDLC
internal operating clocks to restart and stabilize before normal communications can resume. Therefore,
the BDLC is not guaranteed to receive that message correctly.
NOTE
It is important to ensure all transmissions are complete or aborted prior to
putting the BDLC into stop mode.