Datasheet

Electrical Specifications
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 367
28.1.4 5.0 Volt DC Electrical Characteristics
Characteristic
(1)
1. V
DD
= 5.0 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= –40°C to +T
A
(MAX), unless otherwise noted.
Symbol Min Typical Max Unit
Output High Voltage
(I
LOAD
= –2.0 mA) All Ports
(I
LOAD
= –5.0 mA) All Ports
V
OH
V
DD
–0.8
V
DD
–1.5
—
—
—
—
V
Total source current
I
OH
(TOT)
——10mA
Output Low Voltage
(I
LOAD
= 1.6 mA) All Ports
(I
LOAD
= 10.0 mA) All Ports
V
OL
—
—
—
—
0.4
1.5
V
Total sink current
I
OL
(TOT)
——15mA
Input High Voltage
All Ports, IRQ
s, RST, OSC1
V
IH
0.7 x V
DD
—
V
DD
V
Input Low Voltage
All Ports, IRQ
s, RST, OSC1
V
IL
V
SS
—
0.3 x V
DD
V
V
DD
Supply Current
Run
(2)
Wait
(3)
Stop
(4)
LVI enabled, T
A
= 25°C
LVI disabled, T
A
= 25°C
LVI enabled, –40°C to +125°C
LVI disabled, –40°C to +125°C
2. Run (Operating) I
DD
measured using external square wave clock source (f
BUS
= 8.4 MHz). All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run I
DD
. Measured with all
modules enabled. Typical values at midpoint of voltage range, 25°C only.
3. Wait I
DD
measured using external square wave clock source (f
BUS
= 8.4 MHz). All inputs 0.2 Vdc from rail. No dc loads. Less than 100 pF on
all outputs, C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait I
DD
. Measured with all modules
enabled. Typical values at midpoint of voltage range, 25°C only.
4. Stop I
DD
measured with OSC1 = V
SS
.
I
DD
(5)
5. Although I
DD
is proportional to bus frequency, a current of several mA is present even at very low frequencies.
—
—
—
—
—
—
25
14
100
35
35
20
400
50
500
100
mA
mA
μA
μA
μA
μA
I/O Ports Hi-Z Leakage Current
I
L
–1 — 1 μA
Input Current
I
IN
–1 — 1 μA
Capacitance
Ports (As Input or Output)
C
OUT
C
IN
—
—
—
12
8
pF
Low-Voltage Reset Inhibit (trip)
(recover)
V
LVI
3.80
—
—
—
—
4.49
V
POR ReArm Voltage
(6)
6. Maximum is highest voltage that POR is guaranteed.
V
POR
0 — 200 mV
POR Reset Voltage
(7)
7. Maximum is highest voltage that POR is possible.
V
PORRST
0 — 800 mV
POR Rise Time Ramp Rate
(8)
8. If minimum V
DD
is not reached before the internal POR reset is released, RST must be driven low externally until minimum V
DD
is reached.
R
POR
0.02 — — V/ms
High COP Disable Voltage
(9)
9. See 15.8 COP Module During Break Interrupts. V
HI
applied to RST.
V
HI
V
DD
+ 3.0
—
V
DD
+ 4.5
V
Monitor mode entry voltage on IRQ
(10)
10. See Monitor mode description within Chapter 15 Computer Operating Properly (COP). V
HI
applied to IRQ or RST
V
HI
V
DD
+ 3.0
—
V
DD
+ 4.5
V
Pull resistor (KBD[4:0])
R
PU
— 100 — kΩ