Datasheet

Electrical Specifications
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 369
28.1.7 5.0 Vdc ± 0.5 V Serial Peripheral Interface (SPI) Timing
Num
(1)
1. Item numbers refer to dimensions in Figure 28-1 and Figure 28-2.
Characteristic
(2)
2. All timing is shown with respect to 30% V
DD
and 70% V
DD
, unless otherwise noted; assumes 100 pF load on all SPI pins.
Symbol Min Max Unit
Operating Frequency
(3)
Master
Slave
3. f
BUS
= the currently active bus frequency for the microcontroller.
f
BUS(M)
f
BUS(S)
f
BUS
/128
dc
f
BUS
/2
f
BUS
MHz
1
Cycle Time
Master
Slave
t
cyc(M)
t
cyc(S)
2
1
128
—
t
cyc
2 Enable Lead Time
t
Lead
15 — ns
3 Enable Lag Time
t
Lag
15 — ns
4
Clock (SCK) High Time
Master
Slave
t
W(SCKH)M
t
W(SCKH)S
100
50
—
—
ns
5
Clock (SCK) Low Time
Master
Slave
t
W(SCKL)M
t
W(SCKL)S
100
50
—
—
ns
6
Data Setup Time (Inputs)
Master
Slave
t
SU(M)
t
SU(S)
45
5
—
—
ns
7
Data Hold Time (Inputs)
Master
Slave
t
H(M)
t
H(S)
0
15
—
—
ns
8
Access Time, Slave
(4)
CPHA = 0
CPHA = 1
4. Time to data active from high-impedance state.
t
A(CP0)
t
A(CP1)
0
0
40
20
ns
9 Slave Disable Time (Hold Time to High-Impedance State)
t
DIS
—25ns
10
Enable Edge Lead Time to Data Valid
(5)
Master
Slave
5. With 100 pF on all SPI pins.
t
EV(M)
t
EV(S)
—
—
10
40
ns
11
Data Hold Time (Outputs, after Enable Edge)
Master
Slave
t
HO(M)
t
HO(S)
0
5
—
—
ns
12
Data Valid
Master (Before Capture Edge)
t
V(M)
90 — ns
13
Data Hold Time (Outputs)
Master (Before Capture Edge)
t
HO(M)
100 — ns