Datasheet

Electrical Specifications
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
370 Freescale Semiconductor
Figure 28-1. SPI Master Timing Diagram
NOTE
NOTE: This first clock edge is generated internally, but is not seen at the SCK pin.
SS pin of master held high.
MSB IN
SS
(INPUT)
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
NOTE
4
5
5
1
4
BITS 6–1 LSB IN
MASTER MSB OUT BITS 6–1 MASTER LSB OUT
10 11 10 11
76
NOTE
NOTE: This last clock edge is generated internally, but is not seen at the SCK pin.
SS pin of master held high.
MSB IN
SS
(INPUT)
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
NOTE
4
5
5
1
4
BITS 6–1 LSB IN
MASTER MSB OUT BITS 6–1 MASTER LSB OUT
10 11
10 11
76
a) SPI Master Timing (CPHA = 0)
b) SPI Master Timing (CPHA = 1)
12
13
12
13