Datasheet

Electrical Specifications
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor 373
28.1.10 CGM Acquisition/Lock Time Information
Description
(1)
1. V
DD
= 5.0 Vdc ± 0.5 V, V
SS
= 0 Vdc, T
A
= –40°C to T
A
(MAX), unless otherwise noted.
Symbol Min
Typ
(2)
2. Conditions for typical and maximum values are for Run mode with f
CGMXCLK
= 8 MHz, f
BUSDES
= 8 MHz, N = 4, L = 7, discharged C
F
= 15 nF,
V
DD
= 5 Vdc.
Max
(2)
Unit Notes
Manual Mode Time to Stable
t
ACQ
—
(8 x V
DDA
) /
(f
CGMXCLK
x K
ACQ)
—s
If C
F
Chosen
Correctly
Manual Stable to Lock Time
t
AL
—
(4 x V
DDA
) /
(f
CGMXCLK
x K
TRK
)
—s
If C
F
Chosen
Correctly
Manual Acquisition Time
t
LOCK
—
t
ACQ
+t
AL
—s
Tracking Mode Entry Frequency
Tolerance
D
TRK
0—± 3.6 %
Acquisition Mode Entry
Frequency Tolerance
D
UNT
± 6.3 — ± 7.2 %
LOCK Entry Freq. Tolerance
D
LOCK
0—± 0.9 %
LOCK Exit Freq. Tolerance
D
UNL
± 0.9 — ± 1.8 %
Reference Cycles per
Acquisition Mode Measurement
n
ACQ
—32——
Reference Cycles per Tracking
Mode Measurement
n
TRK
—128——
Automatic Mode Time to Stable
t
ACQ
n
ACQ
/f
XCLK
(8 x V
DDA
) /
(f
XCLK
x K
ACQ)
s
If C
F
Chosen
Correctly
Automatic Stable to Lock Time
t
AL
n
TRK
/f
XCLK
(4 x V
DDA
) /
(f
XCLK
x K
TRK
)
—s
If C
F
Chosen
Correctly
Automatic Lock Time
t
LOCK
—0.6525ms
PLL Jitter, Deviation of Average
Bus Frequency over 2 ms
(3)
3. Guaranteed by not tested. Refer to Chapter 10 Clock Generator Module (CGM) for guidance on the use of the PLL.
0—
± (f
CRYS
)
x (.025%)
x (N/4)
%
N = VCO Freq.
Mult.
K value for automatic mode
time to stable
K
acq
—0.2——
K value
K
trk
— 0.004 — —