Datasheet

Electrical Specifications
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
376 Freescale Semiconductor
28.1.15 BDLC Transmitter VPW Symbol Timings
28.1.16 BDLC Receiver VPW Symbol Timings
Characteristic
(1), (2) (3)
1. f
BDLC
= 1.048576 or 1.0 MHz, V
DD
= 5.0 V ± 10%, V
SS
= 0 V
2. See Figure 28-3.
3.
Transmit timing dependent upon BARD register matching physical transceiver timing.
Number Symbol Min Typ Max Unit
Passive Logic 0 10
t
TVP1
62 64 66 μs
Passive Logic 1 11
t
TVP2
126 128 130 μs
Active Logic 0 12
t
TVA1
126 128 130 μs
Active Logic 1 13
t
TVA2
62 64 66 μs
Start-of-Frame (SOF) 14
t
TVA3
198 200 202 μs
End-of-Data (EOD) 15
t
TVP3
198 200 202 μs
End-of-Frame (EOF) 16
t
TV4
278 280 282 μs
Inter-Frame Separator (IFS) 17
t
TV6
298 300 — μs
Characteristic
(1), (2), (3)
1. f
BDLC
= 1.048576 or 1.0 MHz, V
DD
= 5.0 V ± 10%, V
SS
= 0 V
2. The receiver symbol timing boundaries are subject to an uncertainty of 1 t
BDLC
μs due to sampling considerations.
3. See Figure 28-3.
Number Symbol Min Typ Max Unit
Passive Logic 0 10
t
TRVP1
34 64 96 μs
Passive Logic 1 11
t
TRVP2
96 128 163 μs
Active Logic 0 12
t
TRVA1
96 128 163 μs
Active Logic 1 13
t
TRVA2
34 64 96 μs
Start-of-Frame (SOF) 14
t
TRVA3
163 200 239 μs
End-of-Data (EOD) 15
t
TRVP3
163 200 239 μs
End-of-Frame (EOF) 16
t
TRV4
239 280 320 μs
Break 18
t
TRV6
280 — — μs