MC68HC908GP32 Data Sheet M68HC08 Microcontrollers MC68HC908GP32 Rev. 10 1/2008 freescale.
MC68HC908GP32 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History Revision History Date July, 2001 August, 2002 August, 2005 March, 2006 Revision Level Page Number(s) Description In Table 15-1, second cell in "Comment" column, corrected PTC to PTC1. 199 In Figure 21-2, Timebase control register, bit 0 is a reserved bit. 337 Updated crystal oscillator component values in 23.17.1 CGM Component Specifications. 387 Added appendix A: MC68HC08GP32 — ROM part. 397 Section 22.
Revision History Date January, 2008 Revision Level Description Page Number(s) Figure 13-5. SCI Receiver Block Diagram — Replaced SCI receiver block diagram 138 Chapter 14 System Integration Module (SIM) — Corrected Break interrupt and SBSW bit descriptions 157 14.7.
Revision History MC68HC908GP32 Data Sheet, Rev.
List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Chapter 3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Chapter 4 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Chapters MC68HC908GP32 Data Sheet, Rev.
Table of Contents Chapter 1 General Description 1.1 1.2 1.2.1 1.2.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 1.5.12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Features of the MC68HC908GP32 . . . . . . . . . . . . . . . . .
Table of Contents Chapter 3 Low-Power Modes 3.1 3.1.1 3.1.2 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 3.8 3.8.1 3.8.2 3.9 3.9.1 3.9.2 3.10 3.10.1 3.10.2 3.11 3.11.1 3.11.2 3.12 3.12.1 3.12.2 3.13 3.13.1 3.13.2 3.14 3.15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 4 Analog-to-Digital Converter (ADC) 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.4 4.5 4.5.1 4.5.2 4.6 4.6.1 4.6.2 4.6.3 4.7 4.7.1 4.7.2 4.7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 5.4.10 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.6 5.7 5.7.1 5.7.2 5.7.3 5.8 5.8.1 5.8.2 5.8.3 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 8 Central Processor Unit (CPU) 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.4 8.5 8.5.1 8.5.2 8.6 8.7 8.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 10.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7 KBI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 13 Serial Communications Interface Module (SCI) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 Functional Description . .
Table of Contents 14.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . .
15.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.11 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 17.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . .
.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.13 5.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.14 3.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents MC68HC908GP32 Data Sheet, Rev.
Chapter 1 General Description 1.1 Introduction The MC68HC908GP32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 1.2 Features For convenience, features have been organized to reflect: • Standard features of the MC68HC908GP32 • Features of the CPU08 1.2.
General Description • • • • • • • • • • • • • • • • Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, and PWM capability on each channel 8-channel, 8-bit successive approximation analog-to-digital converter (ADC) BREAK module (BRK) to allow single breakpoint setting during in-circuit debugging Internal pullups on IRQ and RST to reduce customer system cost Clock generator module with on-chip 32-kHz crystal compatible PLL (phase-lock loop) Up to
MCU Block Diagram 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908GP32. Text in parentheses within a module block indicates the module name. Text in parentheses next to a signal indicates the module which uses the signal.
General Description 1.
Pin Assignments VDDA (PLL) 1 42 PTA7/KBD7 VSSA (PLL) 2 41 PTA6/KBD6 CGMXFC (PLL) 3 40 PTA5/KBD5 OSC2 4 39 PTA4/KBD4 OSC1 5 38 PTA3/KBD3 RST 6 37 PTA2/KBD2 PTC0 7 36 PTA1/KBD1 PTC1 8 35 PTA0/KBD0 PTC2 9 34 VSSAD/VREFL (ADC) PTC3 10 33 VDDAD/VREFH (ADC) PTC4 11 32 PTB7/AD7 PTE0/TxD 12 31 PTB6/AD6 PTE1/RxD 13 30 PTB5/AD5 IRQ 14 29 PTB4/AD4 PTD0/SS 15 28 PTB3/AD3 PTD1/MISO 16 27 PTB2/AD2 PTD2/MOSI 17 26 PTB1/AD1 PTD3/SPSCK 18 25 PTB0/AD0 V
34 PTA2/KBD2 PTA3/KBD3 PTA6/KBD6 38 35 PTA7/KBD7 39 PTA4/KBD4 VDDA 40 36 VSSA 41 PTA5/KBD5 CGMXFC 42 37 OSC2 RST 1 43 44 OSC1 General Description 33 PTA1/KBD1 28 PTB6/AD6 PTC5 7 27 PTB5/AD5 PTC6 8 26 PTB4/AD4 PTE0/TxD 9 25 PTB3/AD3 PTE1/RxD 10 24 PTB2/AD2 23 PTB1/AD1 PTB0/AD0 22 PTD0/SS 12 IRQ 11 21 6 PTD7/T2CH1 PTC4 20 PTB7/AD7 PTD6/T2CH0 29 19 5 PTD5/T1CH1 PTC3 18 VDDAD/VREFH PTD4/T1CH0 30 17 4 VDD PTC2 16 VSSAD/VREFL VSS 31 15 3 PTD3/SPSCK
Pin Functions MCU VDD VSS C1 0.1 µF + C2 VDD NOTE: Component values shown represent typical applications. Figure 1-5. Power Supply Bypassing 1.5.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Chapter 5 Clock Generator Module (CGM). 1.5.3 External Reset Pin (RST) A low on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system.
General Description Decoupling of these pins should be as per the digital supply. See Chapter 4 Analog-to-Digital Converter (ADC). VREFH is the high reference supply for the ADC, and is internally connected to VDDAD. VREFL is the low reference supply for the ADC, and is internally connected to VSSAD. 1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0) PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port A pins can be programmed to serve as keyboard interrupt pins.
Chapter 2 Memory 2.1 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • 32,256 bytes of user FLASH memory • 512 bytes of random-access memory (RAM) • 36 bytes of user-defined vectors • 307 bytes of monitor ROM 2.2 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset. In the memory map (Figure 2-1) and in register figures in this document, unimplemented locations are shaded. 2.
Memory $0000 ↓ $003F $0040 ↓ $023F $0240 ↓ $7FFF $8000 ↓ $FDFF RAM 512 Bytes Unimplemented 32,192 Bytes FLASH Memory 32,256 Bytes $FE00 SIM Break Status Register (SBSR) $FE01 SIM Reset Status Register (SRSR) $FE02 Reserved (SUBAR) $FE03 SIM Break Flag Control Register (SBFCR) $FE04 Interrupt Status Register 1 (INT1) $FE05 Interrupt Status Register 2 (INT2) $FE06 Interrupt Status Register 3 (INT3) $FE07 Reserved $FE08 FLASH Control Register (FLCR) $FE09 Break Address Register High (BRKH)
Input/Output (I/O) Section Addr.
Memory Addr.
Input/Output (I/O) Section Addr.
Memory Addr.
Input/Output (I/O) Section Addr.
Memory Addr.
Input/Output (I/O) Section . Table 2-1.
Memory 2.5 Random-Access Memory (RAM) This section describes the 512 bytes of RAM (random-access memory). Addresses $0040 through $023F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 192 bytes of RAM.
FLASH Memory NOTE A security feature prevents viewing of the FLASH contents.(1) 2.6.2 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations. Address: Read: $FE08 Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 = Unimplemented Figure 2-3.
Memory 6. 7. 8. 9. 10. Wait for a time, tErase (min. 1 ms or 4 ms) Clear the ERASE bit. Wait for a time, tnvh (min. 5 µs) Clear the HVEN bit. After a time, trcv (typ. 1 µs), the memory can be accessed again in read mode. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps.
FLASH Memory During the programming cycle, make sure that all addresses being written to fit within one of the ranges specified above. Attempts to program addresses in different row ranges in one programming cycle will fail. Use this step-by-step procedure to program a row of FLASH memory (Figure 2-4 is a flowchart representation). NOTE Only bytes which are currently $FF may be programmed. 1. Set the PGM bit.
Memory PGM bit (step 7 to step 10) must not exceed the maximum programming time, tPROG maximum. NOTE Be cautious when programming the FLASH array to ensure that non-FLASH locations are not used as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm. This applies particularly to $FFD4–$FFDF. 2.6.
FLASH Memory 1 Algorithm for programming a row (64 bytes) of FLASH memory 2 3 4 5 6 7 8 Set PGM bit Read the FLASH block protect register Write any data to any FLASH address within the row address range desired Wait for a time, tnvs Set HVEN bit Wait for a time, tpgs Write data to the FLASH address to be programmed Wait for a time, tPROG Completed programming this row? Y N NOTE: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address prog
Memory When the FLBPR is programmed with all 0’s, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase. When bits within the FLBPR are programmed, they lock a block of memory, address ranges as shown in 2.6.6.1 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited.
FLASH Memory Examples of protect start address: BPR[7:0] Start of Address of Protect Range $00 The entire FLASH memory is protected. $01 (0000 0001) $8080 (1000 0000 1000 0000) $02 (0000 0010) $8100 (1000 0001 0000 0000) and so on... $FE (1111 1110) $FF00 (1111 1111 0000 0000) $FF The entire FLASH memory is not protected. Note: The end address of the protected range is always $FFFF. 2.6.
Memory MC68HC908GP32 Data Sheet, Rev.
Chapter 3 Low-Power Modes 3.1 Introduction The MCU may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are entered through instruction execution. This section describes how each module acts in the low-power modes. 3.1.1 Wait Mode The WAIT instruction puts the MCU in a low-power standby mode in which the CPU clock is disabled but the bus clock continues to run.
Low-Power Modes 3.3.2 Stop Mode The break module is inactive in stop mode. The STOP instruction does not affect break module register states. 3.4 Central Processor Unit (CPU) 3.4.1 Wait Mode The WAIT instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock 3.4.
External Interrupt Module (IRQ) 3.6.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. 3.
Low-Power Modes 3.10 Serial Communications Interface Module (SCI) 3.10.1 Wait Mode The SCI module remains active in wait mode. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. 3.10.2 Stop Mode The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states.
Timebase Module (TBM) 3.13 Timebase Module (TBM) 3.13.1 Wait Mode The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during wait mode, reduce the power consumption by stopping the timebase before enabling the WAIT instruction. 3.13.
Low-Power Modes • • • • Serial peripheral interface module (SPI) interrupt — A CPU interrupt request from the SPI loads the program counter with the contents of: – $FFE8 and $FFE9; SPI transmitter – $FFEA and $FFEB; SPI receiver Serial communications interface module (SCI) interrupt — A CPU interrupt request from the SCI loads the program counter with the contents of: – $FFE2 and $FFE3; SCI transmitter – $FFE4 and $FFE5; SCI receiver – $FFE6 and $FFE7; SCI receiver error Analog-to-digital converter modu
Chapter 4 Analog-to-Digital Converter (ADC) 4.1 Introduction This section describes the 8-bit analog-to-digital converter (ADC). 4.2 Features Features of the ADC module include: • Eight channels with multiplexed input • Linear successive approximation with monotonicity • 8-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock 4.
Analog-to-Digital Converter (ADC) INTERNAL DATA BUS READ DDRBx WRITE DDRBx DISABLE DDRBx RESET WRITE PTBx PTBx PTBx ADC CHANNEL x READ PTBx DISABLE ADC DATA REGISTER CONVERSION INTERRUPT COMPLETE LOGIC AIEN ADC ADC VOLTAGE IN (VADIN) CHANNEL SELECT ADCH4–ADCH0 ADC CLOCK COCO CGMXCLK BUS CLOCK CLOCK GENERATOR ADIV2–ADIV0 ADICLK Figure 4-1.
Interrupts 4.3.4 Conversion In continuous conversion mode, the ADC data register will be filled with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO bit is set after the first conversion and will stay set until the next read of the ADC data register. In single conversion mode, conversion begins with a write to the ADSCR.
Analog-to-Digital Converter (ADC) 4.6.2 ADC Analog Ground Pin (VSSAD)/ADC Voltage Reference Low Pin (VREFL) The ADC analog portion uses VSSAD as its ground pin. Connect the VSSAD pin to the same voltage potential as VSS. NOTE Route VSSAD cleanly to avoid any offset errors. 4.6.3 ADC Voltage In (VADIN) VADIN is the input voltage signal from one of the eight ADC channels to the ADC module. 4.
I/O Registers ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is completed between writes to the ADSCR when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH4–ADCH0 — ADC Channel Select Bits ADCH4–ADCH0 form a 5-bit field which is used to select one of 16 ADC channels. Only eight channels, AD7–AD0, are available on this MCU.
Analog-to-Digital Converter (ADC) 4.7.2 ADC Data Register One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC conversion completes. Address: Read: $003D Bit 7 6 5 4 3 2 1 Bit 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 4-3. ADC Data Register (ADR) 4.7.3 ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC.
I/O Registers ADICLK — ADC Input Clock Select Bit ADICLK selects either the bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be guaranteed.
Analog-to-Digital Converter (ADC) MC68HC908GP32 Data Sheet, Rev.
Chapter 5 Clock Generator Module (CGM) 5.1 Introduction This section describes the clock generator module. The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.
Clock Generator Module (CGM) OSCILLATOR (OSC) OSC2 CGMXCLK (TO: SIM, TIMTB15A, ADC) OSC1 SIMOSCEN (FROM SIM) OSCSTOPENB (FROM CONFIG) PHASE-LOCKED LOOP (PLL) CGMRDV REFERENCE DIVIDER CGMRCLK CLOCK SELECT CIRCUIT BCS R RDS3–RDS0 VDDA CGMXFC ÷2 A CGMOUT B S* (TO SIM) *WHEN S = 1, CGMOUT = B VSSA SIMDIV2 (FROM SIM) VPR1–VPR0 VRS7–VRS0 L VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER PHASE DETECTOR 2E CGMVCLK PLL ANALOG AUTOMATIC MODE CONTROL LOCK DETECTOR LOCK AUTO MUL11–MUL0 N CGMVDV F
Functional Description 5.3.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency.
Clock Generator Module (CGM) The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external capacitor connected to CGM/XFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, described in 5.3.4 Acquisition and Tracking Modes.
Functional Description • • The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance. (See 5.8 Acquisition/Lock Time Specifications for more information.) CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling the LOCK bit. (See 5.5.1 PLL Control Register.) The PLL also may operate in manual mode (AUTO = 0).
Clock Generator Module (CGM) When the tolerance on the bus frequency is tight, choose fRCLK to an integer divisor of fBUSDES, and R = 1. If fRCLK cannot meet this requirement, use the following equation to solve for R with practical choices of fRCLK, and choose the fRCLK that gives the lowest R. ⎛ f VCLKDES⎞ ⎫ ⎧ ⎛ f VCLKDES⎞ R = round R MAX × ⎨ ⎜ --------------------------⎟ – integer ⎜ --------------------------⎟ ⎬ ⎝ f RCLK ⎠ ⎭ ⎩ ⎝ f RCLK ⎠ 4. Select a VCO frequency multiplier, N.
Functional Description 9. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, fVRS. The center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL. E f VRS = ( L × 2 )f NOM For proper operation, E f NOM × 2 f VRS – f VCLK ≤ ---------------------------2 10. Verify the choice of P, R, N, E, and L by comparing fVCLK to fVRS and fVCLKDES.
Clock Generator Module (CGM) 5.3.7 Special Programming Exceptions The programming method described in 5.3.6 Programming the PLL does not account for three possible exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for these exceptions: • A 0 value for R or N is interpreted exactly the same as a value of 1. • A 0 value for L disables the PLL and prevents its selection as the source for the base clock. (See 5.3.8 Base Clock Selector Circuit.) 5.3.
I/O Signals SIMOSCEN OSCSTOPENB (FROM CONFIG) CGMXCLK OSC1 OSC2 VSSA CGMXFC VDDA VDD RB 10 kΩ RS 0.01 µF CBYP 0.1 µF 0.033 µF X1 C1 C2 Note: Filter network in box can be replaced with a 0.47µF capacitor, but will degrade stability. Figure 5-2. CGM External Connections 5.4 I/O Signals The following paragraphs describe the CGM I/O signals. 5.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 5.4.
Clock Generator Module (CGM) 5.4.4 PLL Analog Power Pin (VDDA) VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage potential as the VDD pin. NOTE Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 5.4.5 PLL Analog Ground Pin (VSSA) VSSA is a ground pin used by the analog portions of the PLL. Connect the VSSA pin to the same voltage potential as the VSS pin.
CGM Registers 5.5 CGM Registers These registers control and monitor operation of the CGM: • PLL control register (PCTL) (See 5.5.1 PLL Control Register.) • PLL bandwidth control register (PBWC) (See 5.5.2 PLL Bandwidth Control Register.) • PLL multiplier select register high (PMSH) (See 5.5.3 PLL Multiplier Select Register High.) • PLL multiplier select register low (PMSL) (See 5.5.4 PLL Multiplier Select Register Low.) • PLL VCO range select register (PMRS) (See 5.5.5 PLL VCO Range Select Register.
Clock Generator Module (CGM) 5.5.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits. Address: $0036 Bit 7 Read: Write: Reset: PLLIE 0 6 PLLF 5 4 3 2 1 Bit 0 PLLON BCS PRE1 PRE0 VPR1 VPR0 1 0 0 0 0 0 0 = Unimplemented Figure 5-4.
CGM Registers if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. (See 5.3.8 Base Clock Selector Circuit.) PRE1 and PRE0 — Prescaler Program Bits These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See 5.3.3 PLL Circuits and 5.3.6 Programming the PLL.
Clock Generator Module (CGM) Address: $0037 Bit 7 Read: Write: Reset: AUTO 0 6 5 LOCK ACQ 0 0 = Unimplemented 4 3 2 1 0 0 0 0 0 0 0 0 R Bit 0 R 0 = Reserved Figure 5-5. PLL Bandwidth Control Register (PBWC) AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
CGM Registers the multiplier select registers configures the modulo feedback divider the same as a value of $0001. Reset initializes the registers to $0040 for a default multiply value of 64. NOTE The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). Bit7–Bit4 — Unimplemented Bits These bits have no function and always read as logic 0s. 5.5.
Clock Generator Module (CGM) PCTL is set. (See 5.3.7 Special Programming Exceptions.) A value of $00 in the VCO range select register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See 5.3.8 Base Clock Selector Circuit and 5.3.7 Special Programming Exceptions.). Reset initializes the register to $40 for a default range multiply value of 64.
Special Modes interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as logic 0. Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL.
Clock Generator Module (CGM) 5.8 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 5.8.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input.
Acquisition/Lock Time Specifications Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause drastic changes in the operation of the PLL.
Clock Generator Module (CGM) MC68HC908GP32 Data Sheet, Rev.
Chapter 6 Configuration Register (CONFIG) 6.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options: • Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) • COP timeout period (262,128 or 8176 CGMXCLK cycles) • STOP instruction • Computer operating properly module (COP) • Low-voltage inhibit (LVI) module control and voltage trip point selection • Enable/disable the oscillator (OSC) during stop mode 6.
Configuration Register (CONFIG) Address: Read: Write: Reset: $001F Bit 7 6 5 4 3 2 1 Bit 0 COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD 0 0 0 0 See Note 0 0 0 Note: LVI5OR3 bit is only reset via POR (power-on reset) Figure 6-2. Configuration Register 1 (CONFIG1) OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit OSCSTOPENB enables the oscillator to continue operating during stop mode.
Functional Description LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit LVI5OR3 selects the voltage operating mode of the LVI module. (See Chapter 11 Low-Voltage Inhibit (LVI).) The voltage mode selected for the LVI should match the operating VDD. See Chapter 19 Electrical Specifications for the LVI’s voltage trip points for each of the modes. 1 = LVI operates in 5-V mode. 0 = LVI operates in 3-V mode.
Configuration Register (CONFIG) MC68HC908GP32 Data Sheet, Rev.
Chapter 7 Computer Operating Properly (COP) 7.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register. 7.2 Functional Description Figure 7-1 shows the structure of the COP module.
Computer Operating Properly (COP) The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration register. With a 8176 CGMXCLK cycle overflow option, a 32.768-kHz crystal gives a COP timeout period of 250 ms.
COP Control Register 7.3.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. (See Chapter 6 Configuration Register (CONFIG).) 7.3.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. (See Chapter 6 Configuration Register (CONFIG).) 7.4 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector.
Computer Operating Properly (COP) To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction is disabled, execution of a STOP instruction results in an illegal opcode reset. 7.8 COP Module During Break Mode The COP is disabled during a break interrupt when VTST is present on the RST pin. MC68HC908GP32 Data Sheet, Rev.
Chapter 8 Central Processor Unit (CPU) 8.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 8.
Central Processor Unit (CPU) 7 0 ACCUMULATOR (A) 15 0 H X INDEX REGISTER (H:X) 0 15 STACK POINTER (SP) 0 15 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 8-1. CPU Registers 8.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
CPU Registers 8.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
Central Processor Unit (CPU) 8.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 8-6.
Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
Central Processor Unit (CPU) 8.7 Instruction Set Summary Table 8-1 provides a summary of the M68HC08 instruction set.
Instruction Set Summary BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low Bit Test PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 PC ← (PC) + 2 + rel ? IRQ = 1 PC ← (PC) + 2 + rel ? IRQ = 0 – – – – – – REL – – – – – – REL IMM DIR EXT 0 – – ↕ ↕ – IX2 IX1 IX SP1 SP2 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 (A) & (M) Branch if Less Than or Equal To (Signed Operands) BLO rel
Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP V H I N Z C M ← $00 A ← $00 X ← $00 H ← $00 M ← $00 M ← $00 M ← $00 Clear Compare A with M (A) – (M) Complement (One’s Complement) CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare H:X with M DAA Decimal Adjust A Compare X with M EOR #opr EOR opr EO
Instruction Set Summary JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X OR
Central Processor Unit (CPU) Pull A from Stack Pull H from Stack Pull X from Stack RTI Return from Interrupt RTS Return from Subroutine STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP SP ← (SP + 1); Pull (A) SP ← (SP + 1); Pull (H) SP ← (SP + 1); Pull (X) C Rotate Left through Carry b7 b0 C Rotate Right through Carry b7 SP ← $FF SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (
Opcode Map V H I N Z C SWI Software Interrupt TAP TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS Transfer A to CCR Transfer A to X Transfer CCR to A PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte CCR ← (A) X ← (A) A ← (CCR) Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 WAIT A C CCR dd dd rr DD DIR DIX+
MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
Chapter 9 External Interrupt (IRQ) 9.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 9.2 Features Features of the IRQ module include: • A dedicated external interrupt pin IRQ • IRQ interrupt control bits • Programmable edge-only or edge and level interrupt sensitivity • Automatic interrupt acknowledge • Internal pullup device 9.3 Functional Description A low level applied to the external interrupt request (IRQ) pin can latch a CPU interrupt request.
External Interrupt (IRQ) Interrupt signals on the IRQ pin are latched into the IRQ latch. The IRQ latch remains set until one of the following actions occurs: • IRQ vector fetch. An IRQ vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch. • Software clear. Software can clear the IRQ latch by writing a 1 to ACK in the interrupt status and control register (INTSCR). • Reset. A reset automatically clears the IRQ latch.
Interrupts 9.4 Interrupts The interrupt flag (IRQF) is set when the IRQ pin is asserted based on the IRQ mode. The IRQ interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests. 9.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 9.5.1 Wait Mode The IRQ module remains active in wait mode. Clearing IMASK in INTSCR enables IRQ interrupt requests to bring the MCU out of wait mode. 9.5.
External Interrupt (IRQ) 9.8 Registers The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks the IRQ interrupt request • Controls triggering sensitivity of the IRQ interrupt pin Read: Bit 7 6 5 4 3 2 0 0 0 0 IRQF 0 Write: Reset: ACK 0 0 0 0 0 1 Bit 0 IMASK MODE 0 0 0 = Unimplemented Figure 9-2.
Chapter 10 Keyboard Interrupt (KBI) Module 10.1 Introduction The keyboard interrupt module (KBI) provides independently maskable external interrupts. The KBI shares its pins with general-purpose input/output (I/O) port pins. 10.
Keyboard Interrupt (KBI) Module 10.4 Keyboard Operation Writing to the KBIEx bits in the keyboard interrupt enable register (INTKBIER) independently enables or disables each KBI pin. Enabling a keyboard interrupt pin also enables its internal pullup device irrespective of PUEx bits in the input pullup enable register. A low applied to an enabled keyboard interrupt pin latches a keyboard interrupt request.
Interrupts 10.4.3 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup to pull the pin to a high level. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting IMASKK in INTKBSCR. 2. Enable the KBI pins by setting the appropriate KBIEx bits in INTKBIER. 3. Write to ACKK in INTKBSCR to clear any false interrupts. 4. Clear IMASKK.
Keyboard Interrupt (KBI) Module 10.8 I/O Signals The KBI module can share its pins with the general-purpose I/O pins. 10.8.1 KBI Input Pins (KBI7:KBI0) Each KBI pin is independently programmable as an external interrupt source. Each KBI pin when enabled will automatically configure a pullup device. 10.9 Registers The following registers control and monitor operation of the KBI module: • INTKBSCR (keyboard interrupt status and control register) • INTKBIER (keyboard interrupt enable register) 10.9.
Registers 10.9.2 Keyboard Interrupt Enable Register (INTKBIER) INTKBIER enables or disables each keyboard interrupt pin. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 0 Figure 10-3. Keyboard Interrupt Enable Register (INTKBIER) KBIE7–KBIE0 — Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch KBI interrupt requests.
Keyboard Interrupt (KBI) Module MC68HC908GP32 Data Sheet, Rev.
Chapter 11 Low-Voltage Inhibit (LVI) 11.1 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF. 11.2 Features Features of the LVI module include: • Programmable LVI reset • Selectable LVI trip voltage • Programmable stop mode operation 11.3 Functional Description Figure 11-1 shows the structure of the LVI module. The LVI is enabled out of reset.
Low-Voltage Inhibit (LVI) LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See 6.2 Functional Description for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See 14.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI.
LVI Status Register 11.3.3 Voltage Hysteresis Protection Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS. 11.3.
Low-Voltage Inhibit (LVI) 11.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 11.6.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 11.6.2 Stop Mode If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.
Chapter 12 Input/Output (I/O) Ports 12.1 Introduction Thirty-three (33) bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with pullup devices if configured as input port bits. The pullup devices are automatically and dynamically disabled when a port bit is switched to output mode.
Input/Output (I/O) Ports Addr.
Introduction Table 12-1.
Input/Output (I/O) Ports 12.2 Port A Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI) module. Port A also has software configurable pullup devices if configured as an input port. 12.2.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the eight port A pins.
Port A Figure 12-4 shows the port A I/O logic. READ DDRA ($0004) INTERNAL DATA BUS WRITE DDRA ($0004) DDRAx RESET WRITE PTA ($0000) PTAx PTAx VDD PTAPUEx INTERNAL PULLUP DEVICE READ PTA ($0000) Figure 12-4. Port A I/O Circuit When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
Input/Output (I/O) Ports PTAPUE7–PTAPUE0 — Port A Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port A pin configured to have internal pullup 0 = Corresponding port A pin has internal pullup disconnected 12.3 Port B Port B is an 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter (ADC) module. 12.3.
Port B DDRB7–DDRB0 — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB7–DDRB0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 12-8 shows the port B I/O logic.
Input/Output (I/O) Ports 12.4 Port C Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port. 12.4.1 Port C Data Register The port C data register (PTC) contains a data latch for each of the seven port C pins. NOTE Bit 6 and bit 5 of PTC are not available in a 40-pin dual in-line package and 42-pin shrink dual in-line package.
Port C Figure 12-11 shows the port C I/O logic. NOTE For those devices packaged in a 40-pin dual in-line package and 42-pin shrink dual in-line package, PTC5 and PTC6 are connected to ground internally. DDRC5 and DDRC6 should be set to a 0 to configure PTC5 and PTC6 as inputs. READ DDRC ($0006) INTERNAL DATA BUS WRITE DDRC ($0006) DDRCx RESET WRITE PTC ($0002) PTCx PTCx VDD PTCPUEx READ PTC ($0002) INTERNAL PULLUP DEVICE Figure 12-11.
Input/Output (I/O) Ports 12.4.3 Port C Input Pullup Enable Register The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each of the seven port C pins. Each bit is individually configurable and requires that the data direction register, DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRC is configured for output mode.
Port D T1CH1 and T1CH0 — Timer 1 Channel I/O Bits The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 17 Timer Interface Module (TIM). SPSCK — SPI Serial Clock The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the PTD3/SPSCK pin is available for general-purpose I/O.
Input/Output (I/O) Ports Figure 12-15 shows the port D I/O logic. NOTE For those devices packaged in a 40-pin dual in-line package, PTD6 and PTD7 are not connected. DDRD6 and DDRD7 should be set to a 1 to configure PTD6 and PTD7 as outputs. READ DDRD ($0007) INTERNAL DATA BUS WRITE DDRD ($0007) DDRDx RESET WRITE PTD ($0003) PTDx PTDx VDD PTDPUEx READ PTD ($0003) INTERNAL PULLUP DEVICE Figure 12-15. Port D I/O Circuit When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch.
Port E 12.5.3 Port D Input Pullup Enable Register The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each of the eight port D pins. Each bit is individually configurable and requires that the data direction register, DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRD is configured for output mode.
Input/Output (I/O) Ports RxD — SCI Receive Data Input The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See Chapter 13 Serial Communications Interface Module (SCI). TxD — SCI Transmit Data Output The PTE0/TxD pin is the transmit data output for the SCI module.
Port E When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-6 summarizes the operation of the port E pins. Table 12-6.
Input/Output (I/O) Ports MC68HC908GP32 Data Sheet, Rev.
Chapter 13 Serial Communications Interface Module (SCI) 13.1 Introduction This section describes the serial communications interface (SCI) module, which allows high-speed asynchronous communications with peripheral devices and other MCUs. 13.
Serial Communications Interface Module (SCI) SCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output reflects the name of the shared port pin. Table 13-1 shows the full names and the generic names of the SCI I/O pins. The generic pin names appear in the text of this section. Table 13-1. Pin Name Conventions Generic Pin Names: RxD TxD Full Pin Names: PTE1/RxD PTE0/TxD 13.
Functional Description INTERNAL BUS SCI DATA REGISTER ERROR INTERRUPT CONTROL RECEIVE SHIFT REGISTER PTE1/RxD RECEIVER INTERRUPT CONTROL TRANSMITTER INTERRUPT CONTROL SCI DATA REGISTER TRANSMIT SHIFT REGISTER PTE0/TxD TXINV SCTIE R8 TCIE T8 SCRIE ILIE TE SCTE RE TC RWU SCRF SBK IDLE OR ORIE NF NEIE FE FEIE PE PEIE LOOPS LOOPS SCIBDSRC FROM CONFIG2 FLAG CONTROL RECEIVE CONTROL WAKEUP CONTROL ENSCI ENSCI TRANSMIT CONTROL BKF M RPF WAKE ILTY CGMXCLK BUS CLOCK A SL X B ÷
Serial Communications Interface Module (SCI) Addr.
Functional Description 13.4.2 Transmitter Figure 13-4 shows the structure of the SCI transmitter. The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC. Source selection values are shown in Figure 13-4.
Serial Communications Interface Module (SCI) 13.4.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the PTE0/TxD pin. The SCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1). 2.
Functional Description If the TE bit is cleared during a transmission, the PTE0/TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted. NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin.
Serial Communications Interface Module (SCI) INTERNAL BUS SCP0 SCR0 ÷4 SL = 0 => SCICLK = CGMXCLK SL = 1 => SCICLK = BUS CLOCK PRESCALER BAUD DIVIDER ÷ 16 DATA RECOVERY PTE1/RxD BKF SCI DATA REGISTER H 11-BIT RECEIVE SHIFT REGISTER 8 7 M ILTY PEN ERROR CPU INTERRUPT REQUEST PTY 6 5 4 3 2 1 0 L ALL 0s RPF WAKE START SL X SCR1 STOP CGMXCLK BUS CLOCK SCR2 SCP1 MSB SCIBDSRC FROM CONFIG2 SCRF WAKEUP LOGIC PARITY CHECKING OR ORIE NF NEIE FE FEIE PE PEIE RWU IDLE R8 OR ORIE
Functional Description 13.4.3.3 Data Sampling The receiver samples the PTE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
Serial Communications Interface Module (SCI) To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-3 summarizes the results of the data bit samples. Table 13-3. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification.
Functional Description error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times.
Serial Communications Interface Module (SCI) Fast Data Tolerance Figure 13-8 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10. RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 IDLE OR NEXT CHARACTER RT6 RT5 RT4 RT3 RT2 RECEIVER RT CLOCK RT1 STOP DATA SAMPLES Figure 13-8.
Functional Description Depending on the state of the WAKE bit in SCC1, either of two conditions on the PTE1/RxD pin can bring the receiver out of the standby state: • Address mark — An address mark is a logic 1 in the most significant bit position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF.
Serial Communications Interface Module (SCI) 13.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 13.5.1 Wait Mode The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode.
I/O Registers 13.7.2 PTE1/RxD (Receive Data) The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/RxD pin with port E. When the SCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE). 13.
Serial Communications Interface Module (SCI) TXINV — Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted NOTE Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits. M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 13-5.
I/O Registers Table 13-5. Character Format Selection Control Bits Character Format M PEN and PTY Start Bits Data Bits Parity Stop Bits Character Length 0 0X 1 8 None 1 10 bits 1 0X 1 9 None 1 11 bits 0 10 1 7 Even 1 10 bits 0 11 1 7 Odd 1 10 bits 1 10 1 8 Even 1 11 bits 1 11 1 8 Odd 1 11 bits 13.8.
Serial Communications Interface Module (SCI) ILIE — Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests TE — Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the PTE0/TxD pin.
I/O Registers 13.8.3 SCI Control Register 3 SCI control register 3: • Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted • Enables these interrupts: – Receiver overrun interrupts – Noise error interrupts – Framing error interrupts • Parity error interrupts Address: $0015 Bit 7 Read: R8 Write: Reset: U 6 5 4 3 2 1 Bit 0 T8 R R ORIE NEIE FEIE PEIE U 0 0 0 0 0 0 = Unimplemented R = Reserved U = Unaffected Figure 13-11.
Serial Communications Interface Module (SCI) 13.8.
I/O Registers receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit.
Serial Communications Interface Module (SCI) FE — Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit.
I/O Registers Address: $0017 Bit 7 6 5 4 3 2 Read: 1 Bit 0 BKF RPF 0 0 Write: Reset: 0 0 0 0 0 0 = Unimplemented Figure 13-14. SCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the PTE1/RxD pin. In SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF does not generate a CPU interrupt request.
Serial Communications Interface Module (SCI) Address: $0019 Bit 7 6 Read: Write: Reset: 0 5 4 3 2 1 Bit 0 SCP1 SCP0 R SCR2 SCR1 SCR0 0 0 0 0 0 0 R = Reserved 0 = Unimplemented Figure 13-16. SCI Baud Rate Register (SCBR) SCP1 and SCP0 — SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 13-6. Reset clears SCP1 and SCP0. Table 13-6.
I/O Registers Table 13-8. SCI Baud Rate Selection Examples SCP1 and SCP0 Prescaler Divisor (PD) SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) Baud Rate (fBUS = 4.
Serial Communications Interface Module (SCI) MC68HC908GP32 Data Sheet, Rev.
Chapter 14 System Integration Module (SIM) 14.1 Introduction This section describes the system integration module (SIM). Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 14-1. Table 14-1 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing.
System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO CGM) SIM COUNTER COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) ÷2 CLOCK CONTROL VDD CLOCK GENERATORS INTERNAL CLOCKS INTERNAL PULLUP DEVICE RESET PIN LOGIC LVI (FROM LVI MODULE) POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) SIM RESET STATUS REGISTER RESET INTERRUPT SOURC
SIM Bus Clock Control and Generation Addr.
System Integration Module (SIM) 14.2.1 Bus Timing In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four. 14.2.2 Clock Startup from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed.
Reset and System Initialization CGMOUT RST IAB VECT H VECT L PC Figure 14-4. External Reset Timing 14.3.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles. See Figure 14-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR. (See Figure 14-6.
System Integration Module (SIM) At power-on, these events occur: • A POR pulse is generated. • The internal reset signal is asserted. • The SIM enables CGMOUT. • Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow stabilization of the oscillator. • The RST pin is driven low during the oscillator stabilization time. • The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared.
SIM Counter If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 14.3.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU.
System Integration Module (SIM) 14.5 Exception Control Normal, sequential program execution can be changed in three different ways: • Interrupts: – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts 14.5.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts.
Exception Control FROM RESET BREAK I BIT SET? INTERRUPT? YES NO YES I BIT SET? NO IRQ INTERRUPT? YES NO AS MANY INTERRUPTS AS EXIST ON CHIP STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 14-10. Interrupt Processing MC68HC908GP32 Data Sheet, Rev.
System Integration Module (SIM) 14.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts.
Exception Control 14.5.1.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 14-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 14-3.
System Integration Module (SIM) Bit 0 and Bit 1 — Always read 0 Interrupt Status Register 2 Address: $FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Write: R R R R R R R R 0 0 0 0 0 0 0 0 R = Reserved Reset: Figure 14-13. Interrupt Status Register 2 (INT2) IF14–IF7 — Interrupt Flags 14–7 These flags indicate the presence of interrupt requests from the sources shown in Table 14-3.
Low-Power Modes 14.5.4 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode.
System Integration Module (SIM) Figure 14-16 and Figure 14-17 show the timing for WAIT recovery. IAB $6E0B IDB $A6 $A6 $6E0C $A6 $01 $00FF $0B $00FE $00FD $00FC $6E EXITSTOPWAIT Note: EXITSTOPWAIT = RST pin, CPU interrupt, or break interrupt Figure 14-16. Wait Recovery from Interrupt or Break 32 CYCLES IAB IDB $6E0B $A6 $A6 32 CYCLES RST VCT H RST VCT L $A6 RST CGMXCLK Figure 14-17. Wait Recovery from Internal Reset 14.6.
SIM Registers The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 14-18 shows stop mode entry timing. NOTE To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
System Integration Module (SIM) 14.7.1 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. Address: Read: Write: $FE00 Bit 7 6 5 4 3 2 R R R R R R R = Reserved 1 SBSW Note Reset: Bit 0 R 0 Note: Writing a logic 0 clears SBSW. Figure 14-20. SIM Break Status Register (SBSR) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine.
SIM Registers ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MODRST — Monitor Mode Entry Module Reset Bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ ≠ VTST 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI
System Integration Module (SIM) MC68HC908GP32 Data Sheet, Rev.
Chapter 15 Serial Peripheral Interface Module (SPI) 15.1 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 15.
Serial Peripheral Interface Module (SPI) 15.4 Functional Description Figure 15-1 summarizes the SPI I/O registers and Figure 15-2 shows the structure of the SPI module. Addr.
Functional Description INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER BUSCLK 7 6 5 4 3 2 1 MISO 0 ÷2 MOSI ÷8 CLOCK DIVIDER RECEIVE DATA REGISTER ÷ 32 PIN CONTROL LOGIC ÷ 128 SPMSTR SPE CLOCK SELECT SPR1 SPSCK M CLOCK LOGIC S SS SPR0 SPMSTR TRANSMITTER CPU INTERRUPT REQUEST CPHA MODFEN CPOL SPWOM ERRIE SPI CONTROL SPTIE RECEIVER/ERROR CPU INTERRUPT REQUEST SPRIE SPE SPRF SPTE OVRF MODF Figure 15-2.
Serial Peripheral Interface Module (SPI) 15.4.2 Slave Mode The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode, the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI must be at logic 0. SS must remain low until the transmission is complete. (See 15.7.2 Mode Fault Error.) In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module.
Transmission Formats 15.5.2 Transmission Format When CPHA = 0 Figure 15-4 shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave.
Serial Peripheral Interface Module (SPI) 15.5.3 Transmission Format When CPHA = 1 Figure 15-6 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1.
Queuing Transmission Data SPSCK. This uncertainty causes the variation in the initiation delay shown in Figure 15-7. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
Serial Peripheral Interface Module (SPI) to accept new data. Write to the transmit data register only when the SPTE bit is high. Figure 15-8 shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL = 1:0).
Error Conditions 15.7.1 Overflow Error The overflow flag (OVRF) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. The bit 1 capture strobe occurs in the middle of SPSCK cycle 7. (See Figure 15-4 and Figure 15-6.
Serial Peripheral Interface Module (SPI) BYTE 1 SPI RECEIVE COMPLETE BYTE 2 5 1 BYTE 3 7 BYTE 4 11 SPRF OVRF READ SPSCR 2 READ SPDR 4 3 1 BYTE 1 SETS SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. 3 6 9 8 12 10 14 13 8 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. 9 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 4 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 5 BYTE 2 SETS SPRF BIT.
Interrupts NOTE To prevent bus contention with another master SPI after a mode fault error, clear all SPI bits of the data direction register of the shared I/O port before enabling the SPI. When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission. When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift of the eighth data bit.
Serial Peripheral Interface Module (SPI) Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register. The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1).
Resetting the SPI 15.9 Resetting the SPI Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the following occurs: • The SPTE flag is set. • Any transmission currently in progress is aborted. • The shift register is cleared. • The SPI state counter is cleared, making it ready for a new complete transmission. • All the SPI port logic is defaulted back to being general-purpose I/O.
Serial Peripheral Interface Module (SPI) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits.
I/O Signals 15.12.4 SS (Slave Select) The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission. (See 15.5 Transmission Formats.) Since it is used to indicate the start of a transmission, the SS must be toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low between transmissions for the CPHA = 1 format.
Serial Peripheral Interface Module (SPI) 15.13 I/O Registers Three registers control and monitor SPI operation: • SPI control register (SPCR) • SPI status and control register (SPSCR) • SPI data register (SPDR) 15.13.
I/O Registers 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins SPE — SPI Enable This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 15.9 Resetting the SPI.) Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled SPTIE— SPI Transmit Interrupt Enable This read/write bit enables CPU interrupt requests generated by the SPTE bit.
Serial Peripheral Interface Module (SPI) OVRF — Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. In an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the receive data register. Reset clears the OVRF bit.
I/O Registers SPR1 and SPR0 — SPI Baud Rate Select Bits In master mode, these read/write bits select one of four baud rates as shown in Table 15-4. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Table 15-4. SPI Master Baud Rate Selection SPR1 and SPR0 Baud Rate Divisor (BD) 00 2 01 8 10 32 11 128 Use this formula to calculate the SPI baud rate: BUSCLK Baud rate = -----------------------2 × BD 15.13.
Serial Peripheral Interface Module (SPI) MC68HC908GP32 Data Sheet, Rev.
Chapter 16 Timebase Module (TBM) 16.1 Introduction This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the external crystal clock. This TBM version uses 15 divider stages, eight of which are user selectable. 16.2 Features Features of the TBM module include: • Software programmable 1-Hz, 4-Hz, 16-Hz, 256-Hz, 512-Hz, 1024-Hz, 2048-Hz, and 4096-Hz periodic interrupt using external 32.
Timebase Module (TBM) TBON ÷2 CGMXCLK ÷2 ÷2 ÷2 ÷2 ÷8 ÷2 ÷ 16 ÷2 ÷ 32 ÷ 64 ÷ 128 ÷2 ÷2 ÷2 ÷2 ÷ 2048 ÷2 ÷ 8192 TACK ÷2 TBR0 ÷2 TBR1 ÷2 TBR2 TBMINT ÷ 32768 TBIF 000 TBIE R 001 010 011 SEL 100 101 110 111 Figure 16-1. Timebase Block Diagram 16.4 Timebase Register Description The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the rate.
Interrupts TBR2:TBR0 — Timebase Rate Selection These read/write bits are used to select the rate of timebase interrupts as shown in Table 16-1. Table 16-1. Timebase Rate Selection for OSC1 = 32.768-kHz TBR2 TBR1 TBR0 Divider 0 0 0 0 0 0 0 Timebase Interrupt Rate Hz ms 32768 1 1000 1 8192 4 250 1 0 2048 16 62.5 1 1 128 256 ~ 3.9 1 0 0 64 512 ~2 1 0 1 32 1024 ~1 1 1 0 16 2048 ~0.5 1 1 1 8 4096 ~0.
Timebase Module (TBM) 16.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 16.6.1 Wait Mode The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during wait mode, reduce the power consumption by stopping the timebase before enabling the WAIT instruction. 16.6.
Chapter 17 Timer Interface Module (TIM) 17.1 Introduction This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 17-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2. 17.
Timer Interface Module (TIM) 17.4 Functional Description Figure 17-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence.
Functional Description Addr.
Timer Interface Module (TIM) Addr.
Functional Description 17.4.1 TIM Counter Prescaler The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register select the TIM clock source. 17.4.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs.
Timer Interface Module (TIM) control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered output compare operation, do not write new output compare values to the currently active channel registers.
Functional Description 17.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 17.4.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods.
Timer Interface Module (TIM) 17.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3.
Interrupts 17.5 Interrupts The following TIM sources can generate interrupt requests: • TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. • TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x.
Timer Interface Module (TIM) 17.8 I/O Signals Port D shares four of its pins with the TIM. The four TIM channel I/O pins are T1CH0, T1CH1, T2CH0, and T2CH1 as described in 17.3 Pin Name Conventions. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins. 17.9 I/O Registers NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number.
I/O Registers TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP — TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
Timer Interface Module (TIM) NOTE If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break. Address: T1CNTH, $0021 and T2CNTH, $002C Read: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 17-5.
I/O Registers 17.9.
Timer Interface Module (TIM) MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit.
I/O Registers NOTE Before enabling a TIM channel register for input capture operation, make sure that the PTDx/TCHx pin is stable for at least two bus clocks. TOVx — Toggle On Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit.
Timer Interface Module (TIM) Address: T1CH0H, $0026 and T2CH0H, $0031 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Reset: Indeterminate after reset Figure 17-12. TIM Channel 0 Register High (TCH0H) Address: T1CH0L, $0027 and T2CH0L $0032 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Reset: Indeterminate after reset Figure 17-13.
Chapter 18 Development Support 18.1 Introduction This section describes the break module, the monitor module (MON), and the monitor mode entry methods. 18.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
Development Support ADDRESS BUS[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR ADDRESS BUS[15:0] BKPT (TO SIM) CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW ADDRESS BUS[7:0] Figure 18-1. Break Module Block Diagram Addr. $FE00 Register Name Bit 7 SIM Break Status Register Read: (SBSR) Write: See page 218. Reset: Read: Reserved Write: $FE02 Reset: $FE03 SIM Break Flag Control Read: Register (SBFCR) Write: See page 219.
Break Module (BRK) When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt timing is: • When a break address is placed at the address of the instruction opcode, the instruction is not executed
Development Support 18.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Address: $FE0B Read: Write: Reset: Bit 7 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 18-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit 7. Reset clears the BRKE bit.
Break Module (BRK) 18.2.2.3 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. Address: $FE00 Read: Write: Bit 7 6 5 4 3 2 R R R R R R 1 SBSW Note(1) Reset: Bit 0 R 0 R = Reserved 1. Writing a 0 clears SBSW. Figure 18-6. SIM Break Status Register (SBSR) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine.
Development Support 18.3 Monitor Module (MON) The monitor module allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
Monitor Module (MON) POR RESET NO CONDITIONS FROM Table 18-1 PTA0 = 1, PTA7 = 0 RESET BLANK? IRQ = VTST? YES PTA0 = 1, PTA7 = 0, , PTC0 = 1, PTC1 = 0, AND PTC3 = 1? NO NO YES YES FORCED MONITOR MODE NORMAL USER MODE NORMAL MONITOR MODE FACTORY USE ONLY SEND 8 BYTES SECURITY IS RESET POR? YES NO YES ARE ALL SECURITY BYTES CORRECT? ENABLE FLASH NO DISABLE FLASH MONITOR MODE ENTRY DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) EXECUTE MONITOR CODE YES DOES RESET OCCUR? NO Fi
Development Support VDD RST VDD 0.1 µF 0.1 µF N.C. 9.8304 MHz CLOCK MAX232 4 1 µF + 16 C1– 15 4 C2+ + 5 C2– 10 kΩ PTC3 5 7 10 8 9 IRQ VDD 10 kΩ PTA7 9.1 V 10 kΩ + 74HC125 5 6 DB9 3 PTC1 + V– 6 10 kΩ 1 kΩ V+ 2 1 µF 10 kΩ PTC0 VTST 2 VDD OSC1 0.1 µF 5 1 µF OSC2 VDD C1+ VDDA 74HC125 3 2 VSS PTA0 VSSA 4 1 Figure 18-9. Standard Monitor Mode MC68HC908GP32 Data Sheet, Rev.
Monitor Module (MON) VDD VDDA RST VDD 0.1 µF MAX232 4 1 µF + N.C. 16 C1+ OSC2 9.8304 MHz CLOCK 0.1 µF 5 0.1 µF VDD 15 C1– OSC1 PTC0 N.C. PTC3 N.C. PTC1 N.C. VTST 4 1 µF V+ 2 C2+ + V– 6 5 C2– 1 µF 7 10 3 8 9 IRQ 10 kΩ + 74HC125 5 6 DB9 2 N.C. VDD + 2 74HC125 3 10 kΩ PTA7 PTA0 4 VSS VSSA 1 5 Figure 18-10. Forced Monitor Mode (High) VDD RST VDD 0.1 µF 15 pF MAX232 4 1 µF + C1+ C1– 0.1 µF 330 k OSC2 VDD 16 10 MΩ 15 pF 0.1 µF 5 32.
Development Support Table 18-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode must be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. If $FFFE and $FFFF does not contain $FF (programmed state): – The external clock is 4.9152 MHz with PTC3 low or 9.8304 MHz with PTC3 high – IRQ = VTST 2. If $FFFE and $FFFF contain $FF (erased state): – The external clock is 9.
Monitor Module (MON) Table 18-1. Monitor Mode Signal Requirements and Options Mode IRQ User Reset Vector Mode Selection Communication Speed Divider PLL PTA0 PTA7 PTC0 PTC1 PTC3 COP External Bus Clock Frequency Baud Rate VTST VDD or VTST X 1 0 1 0 0 OFF Disabled 4.9152 MHz 2.457 MHz 9600 VTST VDD or VTST X 1 0 1 0 1 OFF Disabled 9.8304 MHz 2.457 MHz 9600 VDD VDD $FFFF (blank) 1 0 X X X OFF Disabled 9.8304 MHz 2.
Development Support event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied to either IRQ or RST.
Monitor Module (MON) 18.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT Figure 18-12. Monitor Data Format 18.3.1.5 Break Signal A start bit (0) followed by nine 0 bits is a break signal.
Development Support FROM HOST 4 ADDRESS HIGH READ READ ADDRESS HIGH 4 1 ADDRESS LOW 1 ADDRESS LOW 4 DATA 1 3, 2 4 ECHO RETURN Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte. Figure 18-14.
Monitor Module (MON) Table 18-4. WRITE (Write Memory) Command Description Operand Data Returned Opcode Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence FROM HOST WRITE ADDRESS HIGH WRITE ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 18-5.
Development Support Table 18-7. READSP (Read Stack Pointer) Command Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence FROM HOST READSP SP HIGH READSP SP LOW ECHO RETURN Table 18-8.
Monitor Module (MON) 18.3.2 Security A security feature discourages unauthorized reading of Flash locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.
Development Support MC68HC908GP32 Data Sheet, Rev.
Chapter 19 Electrical Specifications 19.1 Introduction This section contains electrical and timing specifications. 19.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 19.5 5.0-V DC Electrical Characteristics for guaranteed operating conditions. Characteristic(1) Symbol Value Unit Supply voltage VDD –0.3 to + 6.
Electrical Specifications 19.3 Functional Operating Range Characteristic Operating temperature range Operating voltage range Symbol Value Unit TA –40 to +85 °C VDD 3.0 ±10% 5.0 ±10% V 19.
5.0-V DC Electrical Characteristics 19.5 5.0-V DC Electrical Characteristics Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.8 VDD – 1.5 VDD – 0.8 — — — — — — — — 50 V V V mA IOH2 — — 50 mA IOHT — — 100 mA VOL VOL VOL IOL1 — — — — — — — — 0.4 1.5 1.0 50 V V V mA IOL2 — — 50 mA IOLT — — 100 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.
Electrical Specifications Symbol Min Typ(2) Max Unit RPU 20 45 65 kΩ Capacitance Ports (as input or output) COut CIn — — — — 12 8 pF Monitor mode entry voltage VTST VDD + 2.5 — 9 V Low-voltage inhibit, trip falling voltage VTRIPF 3.90 4.25 4.50 V Low-voltage inhibit, trip rising voltage VTRIPR 4.20 4.35 4.
3.0-V DC Electrical Characteristics 19.6 3.0-V DC Electrical Characteristics Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.3 VDD – 1.0 VDD – 0.5 — — — — — — — — 30 V V V mA IOH2 — — 30 mA IOHT — — 60 mA VOL VOL VOL IOL1 — — — — — — — — 0.3 1.0 0.8 30 V V V mA IOL2 — — 30 mA IOLT — — 60 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.3 × VDD V — — 4.5 1.
Electrical Specifications Symbol Min Typ(2) Max Unit RPU 20 45 65 kΩ Capacitance Ports (as input or output) COut CIn — — — — 12 8 pF Monitor mode entry voltage VTST VDD + 2.5 — 9 V Low-voltage inhibit, trip falling voltage VTRIPF 2.45 2.60 2.70 V Low-voltage inhibit, trip rising voltage VTRIPR 2.55 2.66 2.
5.0-V Control Timing 19.7 5.0-V Control Timing Symbol Min Max Unit fOSC 32 dc 100 32.8 kHz MHz Internal operating frequency fOP (fBUS) — 8.2 MHz Internal clock period (1/fOP) tCYC 122 — ns RST input pulse width low tIRL 100 — ns IRQ interrupt pulse width low (edge-triggered) tILIH 100 — ns IRQ interrupt pulse period tILIL (3) — tCYC Characteristic(1) Frequency of operation Crystal option External clock option(2) Notes: 1.
Electrical Specifications 19.8 3.0-V Control Timing Symbol Min Max Unit fOSC 32 dc 100 16.4 kHz MHz Internal operating frequency fOP (fBUS) — 4.1 MHz Internal clock period (1/fOP) tCYC 244 — ns RST input pulse width low tIRL 200 — ns IRQ interrupt pulse width low (edge-triggered) tILIH 200 — ns IRQ interrupt pulse period tILIL (3) — tCYC Characteristic(1) Frequency of operation Crystal option External clock option(2) Notes: 1.
Output High-Voltage Characteristics 19.9 Output High-Voltage Characteristics 0 –5 IOH (mA) –10 –40 0 25 85 –15 –20 –25 –30 –35 –40 3 3.2 3.4 3.6 VOH (V) 3.8 4.0 4.2 VOH > VDD –0.8 V @ IOH = –2.0 mA VOH > VDD –1.5 V @ IOH = –10.0 mA Figure 19-2. Typical High-Side Driver Characteristics – Port PTA7–PTA0 (VDD = 4.5 Vdc) 0 IOH (mA) –5 –40 0 25 85 –10 –15 –20 –25 1.3 1.5 1.7 1.9 VOH (V) 2.1 2.3 2.5 VOH > VDD –0.3 V @ IOH = –0.6 mA VOH > VDD –1.0 V @ IOH = –4.0 mA Figure 19-3.
Electrical Specifications 0 IOH (mA) –5 –40 0 25 85 –10 –15 –20 –25 1.3 1.5 1.7 1.9 VOH (V) VOH > VDD –0.5 V @ IOH = –4.0 mA 2.1 2.3 2.5 Figure 19-5. Typical High-Side Driver Characteristics – Port PTC4–PTC0 (VDD = 2.7 Vdc) 0 –10 –20 –40 0 25 85 IOH (mA) –30 –40 –50 –60 –70 –80 –90 3 3.2 3.4 3.6 3.8 VOH (V) 4.0 4.2 4.4 4.6 VOH > VDD –0.8 V @ IOH = –2.0 mA VOH > VDD –1.5 V @ IOH = –10.0 mA Figure 19-6.
Output Low-Voltage Characteristics 19.10 Output Low-Voltage Characteristics 35 30 –40 0 25 85 IOL (mA) 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 VOL (V) 1.2 1.4 1.6 VOL < 0.4 V @ IOL = 1.6 mA VOL < 1.5 V @ IOL = 10.0 mA Figure 19-8. Typical Low-Side Driver Characteristics – Port PTA7–PTA0 (VDD = 5.5 Vdc) 14 12 –40 0 25 85 IOL (mA) 10 8 6 4 2 0 0.2 0.4 0.6 0.8 1.0 VOL (V) 1.2 1.4 1.6 VOL < 0.3 V @ IOL = 0.5 mA VOL < 1.0 V @ IOL = 6.0 mA Figure 19-9.
Electrical Specifications 30 IOL (mA) 25 –40 0 25 85 20 15 10 5 0 0.2 0.4 0.6 0.8 1.0 VOL (V) 1.2 1.6 1.4 VOL < 0.8 V @ IOL = 10 mA Figure 19-11. Typical Low-Side Driver Characteristics – Port PTC4–PTC0 (VDD = 2.7 Vdc) 35 30 –40 0 25 85 IOL (mA) 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 VOL (V) 1.2 1.6 1.4 VOL < 0.4 V @ IOL = 1.6 mA VOL < 1.5 V @ IOL = 10.0 mA Figure 19-12. Typical Low-Side Driver Characteristics – Ports PTB7–PTB0, PTC6–PTC5, PTD7–PTD0, and PTE1–PTE0 (VDD = 5.
Typical Supply Currents 19.11 Typical Supply Currents 16 14 12 IDD (mA) 10 8 6 4 5.5 V 3.6 V 2 0 0 1 2 3 4 5 fBUS (MHz) 6 7 8 9 Figure 19-14. Typical Operating IDD, with All Modules Turned On (–40 °C to 85 °C) 5.0 4.5 4.0 IDD (mA) 3.5 3.0 2.5 2.0 1.5 1.0 5.5 V 3.6 V 0.5 0 0 1 2 3 4 fBUS (MHz) 5 6 7 8 Figure 19-15. Typical Wait Mode IDD, with all Modules Disabled (–40 °C to 85 °C) 1.35 1.30 IDD (mA) 1.25 1.20 1.15 1.10 5.5 V 3.6 V 1.
Electrical Specifications 19.12 ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 2.7 (VDD min) 5.5 (VDD max) V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN 0 VDDAD V VADIN ≤ VREFH Resolution BAD 8 8 Bits Absolute accuracy (VREFL = 0 V, VREFH = VDDAD = 5 V ± 10%) AAD — ±1 LSB Includes quantization ADC internal clock fADIC 0.5 1.
5.0-V SPI Characteristics 19.13 5.
Electrical Specifications 19.14 3.
3.0-V SPI Characteristics SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE SPSCK OUTPUT CPOL = 1 NOTE 5 4 5 4 6 MISO INPUT BITS 6–1 MSB IN 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
Electrical Specifications SS INPUT 3 1 SPSCK INPUT CPOL = 0 5 4 2 SPSCK INPUT CPOL = 1 5 4 9 8 MISO INPUT SLAVE MSB OUT 6 MOSI OUTPUT BITS 6–1 7 NOTE 11 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS INPUT 1 SPSCK INPUT CPOL = 0 5 4 2 3 SPSCK INPUT CPOL = 1 8 MISO OUTPUT MOSI INPUT 5 4 10 NOTE 9 SLAVE MSB OUT 6 7 BITS 6–1 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defi
Timer Interface Module Characteristics 19.15 Timer Interface Module Characteristics Characteristic Symbol Min Max Unit tTH, tTL 2 — tcyc tTLTL Note(1) — tcyc tTCL, tTCH tcyc + 5 — ns Timer input capture pulse width Timer input capture period Timer input clock pulse width 1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
Electrical Specifications 19.16 Clock Generation Module Characteristics 19.16.1 CGM Component Specifications Characteristic Symbol Min Typ Max Unit Crystal reference frequency fXCLK 30 32.768 100 kHz Crystal load capacitance(1) CL — 12.5 — pF (2) C1 — 15 — pF Crystal tuning capacitance(2) C2 — 15 — pF Feedback bias resistor RB 1 10 22 MΩ resistor(3) RS 100 330 470 kΩ Crystal fixed capacitance Series Notes: 1. Crystal manufacturer value. 2. Capacitor on OSC1 pin.
Memory Characteristics 19.16.2 CGM Electrical Specifications Description Symbol Min Typ Max Unit VDD 2.7 — 5.5 V T –40 25 85 °C Reference frequency fRDV 30 32.768 100 kHz Range nominal multiplier fNOM — 38.4 — kHz VCO center-of-range frequency(1) fVRS 38.4 k — 40.0 M Hz Medium-voltage VCO center-of-range frequency(2) fVRS 38.4 k — 40.
Electrical Specifications Characteristic Symbol Min Typ Max Unit tMErase 4 — — ms FLASH PGM/ERASE to HVEN setup time tNVS 10 — — µs FLASH high-voltage hold time tNVH 5 — — µs FLASH high-voltage hold time (mass erase) tNVHL 100 — — µs FLASH program hold time tPGS 5 — — µs FLASH program time tPROG 30 — 40 µs FLASH return to read time tRCV(2) 1 — — µs FLASH cumulative program hv period tHV(3) — — 4 ms FLASH endurance — 10 k 100 k — Cycles FLASH data re
Chapter 20 Mechanical Specifications 20.1 Introduction This section gives the dimensions for: • 40-pin plastic dual in-line package (case 711-03) • 42-pin shrink dual in-line package (case 858-01) • 44-pin plastic quad flat pack (case 824A-01) MC68HC908GP32 Data Sheet, Rev.
Chapter 21 Ordering Information 21.1 Introduction This section contains ordering numbers for the MC68HC908GP32. 21.2 MC Order Numbers Table 21-1. MC Order Numbers Operating temperature range Package MC908GP32CPE –40 °C to +85 °C 40-pin PDIP MC908GP32CBE –40 °C to +85 °C 42-pin SDIP MC908GP32CFBE –40 °C to +85 °C 44-pin QFP MC order number MC68HC908GP32 Data Sheet, Rev.
Ordering Information MC68HC908GP32 Data Sheet, Rev.
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