Datasheet

External Interrupt (IRQ)
MC68HC908GP32 Data Sheet, Rev. 10
104 Freescale Semiconductor
9.8 Registers
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks the IRQ interrupt request
• Controls triggering sensitivity of the
IRQ interrupt pin
IRQF — IRQ Flag Bit
This read-only status bit is set when the IRQ interrupt is pending.
1 =
IRQ interrupt pending
0 =
IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads 0.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables the IRQ interrupt request.
1 = IRQ interrupt request disabled
0 = IRQ interrupt request enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the
IRQ pin.
1 =
IRQ interrupt request on falling edges and low levels
0 =
IRQ interrupt request on falling edges only
Bit 7654321Bit 0
Read: 0000IRQF0
IMASK MODE
Write:
ACK
Reset:00000000
= Unimplemented
Figure 9-2. IRQ Status and Control Register (INTSCR)