Datasheet

Low-Voltage Inhibit (LVI)
MC68HC908GP32 Data Sheet, Rev. 10
112 Freescale Semiconductor
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See 6.2
Functional Description for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU
remains in reset until V
DD
rises above a voltage, V
TRIPR
, which causes the MCU to exit reset. See
14.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI. The
output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the
RST pin low to provide low-voltage protection to external peripheral devices.
Figure 11-1. LVI Module Block Diagram
11.3.1 Polled LVI Operation
In applications that can operate at V
DD
levels below the V
TRIPF
level, software can monitor V
DD
by polling
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be at logic 0 to enable the LVI
module, and the LVIRSTD bit must be at logic 1 to disable LVI resets.
11.3.2 Forced Reset Operation
In applications that require V
DD
to remain above the V
TRIPF
level, enabling LVI resets allows the LVI
module to reset the MCU when V
DD
falls below the V
TRIPF
level. In the configuration register, the
LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
Addr. Register Name Bit 7 654321Bit 0
$FE0C LVI Status Register (LVISR)
Read: LVIOUT 0000000
Write:
Reset:00000000
= Unimplemented
Figure 11-2. LVI I/O Register Summary
LOW V
DD
DETECTOR
LVIPWRD
STOP INSTRUCTION
LVISTOP
LVI RESET
LVIOUT
V
DD
> LVI
Trip
= 0
V
DD
≤ LVI
Trip
= 1
FROM CONFIG
FROM CONFIG1
V
DD
FROM CONFIG1
LVIRSTD
LVI5OR3
FROM CONFIG1