Datasheet

SIM Bus Clock Control and Generation
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor 159
14.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 14-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 5 Clock Generator Module
(CGM).)
Figure 14-3. CGM Clock Signals
$FE03
SIM Break Flag Control
Register (SBFCR)
Read:
BCFE RRRRRRR
Write:
Reset: 0
$FE04
Interrupt Status Register 1
(INT1)
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write: RRRRRRRR
Reset:00000000
$FE05
Interrupt Status Register 2
(INT2)
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write: RRRRRRRR
Reset:00000000
$FE06
Interrupt Status Register 3
(INT3)
Read: 000000IF16IF15
Write: RRRRRRRR
Reset:00000000
Addr. Register Name Bit 7 654321Bit 0
= Unimplemented R = Reserved
Figure 14-2. SIM I/O Register Summary (Continued)
÷ 2
BUS CLOCK
GENERATORS
SIM
SIM COUNTER
MONITOR MODE
USER MODE
SIMOSCEN
OSCILLATOR (OSC)
OSC2
OSC1
PHASE-LOCKED LOOP (PLL)
CGMXCLK
CGMRCLK
IT12
CGMOUT
SIMDIV2
PTC3
TO TIMTB15A, ADC
OSCSTOPENB
FROM
CONFIG
TO REST
OF CHIP
IT23
TO REST
OF CHIP