Datasheet

Reset and System Initialization
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor 161
Figure 14-4. External Reset Timing
14.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles.
See Figure 14-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI,
or POR. (See Figure 14-6.)
NOTE
For LVI or POR resets, the SIM cycles through 4096 + 32 CGMXCLK
cycles during which the SIM forces the
RST pin low. The internal reset
signal then follows the sequence from the falling edge of
RST shown in
Figure 14-5.
Figure 14-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
Figure 14-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
14.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (
RST) is held low while the SIM counter counts out
4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
RST
IAB
PC
VECT H VECT L
CGMOUT
IRST
RST
RST PULLED LOW BY MCU
IAB
32 CYCLES 32 CYCLES
VECTOR HIGH
CGMXCLK
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET