Datasheet

SIM Registers
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor 171
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 14-18 shows stop mode entry timing.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
Figure 14-18. Stop Mode Entry Timing
Figure 14-19. Stop Mode Recovery from Interrupt or Break
14.7 SIM Registers
The SIM has three memory-mapped registers. Table 14-4 shows the mapping of these registers.
Table 14-4. SIM Registers
Address Register Access Mode
$FE00 SBSR User
$FE01 SRSR User
$FE03 SBFCR User
STOP ADDR + 1 SAME SAMEIAB
IDB
PREVIOUS DATA NEXT OPCODE SAME
STOP ADDR
SAME
R/
W
CPUSTOP
Note : Previous data can be operand data or the STOP opcode, depending
on the last instruction.
CGMXCLK
INT/BREAK
IAB STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3
STOP +1
STOP RECOVERY PERIOD