Datasheet

Timer Interface Module (TIM)
MC68HC908GP32 Data Sheet, Rev. 10
200 Freescale Semiconductor
17.4 Functional Description
Figure 17-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter
that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM counter modulo registers,
TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value
at any time without affecting the counting sequence.
The two TIM channels (per timer) are programmable independently as input capture or output compare
channels. If a channel is configured as input capture, then an internal pullup device may be enabled for
that channel. (See 12.5.3 Port D Input Pullup Enable Register.)
Figure 17-1. TIM Block Diagram
Figure 17-2 summarizes the timer registers.
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TSC may generically refer to both
T1SC and T2SC.
MS1A
CH0F
PRESCALER
PRESCALER SELECT
INTERNAL
16-BIT COMPARATOR
PS2 PS1 PS0
16-BIT COMPARATOR
16-BIT LATCH
TCH0H:TCH0L
TOF
TOIE
16-BIT COMPARATOR
16-BIT LATCH
TCH1H:TCH1L
CHANNEL 0
CHANNEL 1
TMODH:TMODL
TRST
TSTOP
TOV0
CH0IE
TOV1
CH1IE
CH1MAX
CH0MAX
16-BIT COUNTER
INTERNAL BUS
BUS CLOCK
T[1,2]CH0
T[1,2]CH1
INTERRUPT
LOGIC
PORT
LOGIC
INTERRUPT
LOGIC
INTERRUPT
LOGIC
PORT
LOGIC
ELS0AELS0B
ELS1AELS1B
MS0B
CH1F
MS0A