Datasheet

Break Module (BRK)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor 219
18.2.2.3 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait
mode. This register is only used in emulation mode.
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
18.2.2.4 SIM Break Flag Control Register
The SIM break control register (SBFCR) contains a bit that enables software to clear status bits while the
MCU is in a break state.
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
18.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes. If enabled,
the break module will remain enabled in wait and stop modes. However, since the internal address bus
does not increment in these modes, a break interrupt will never be triggered.
Address: $FE00
Bit 7654321Bit 0
Read:
RRRRRR
SBSW
R
Write: Note
(1)
Reset: 0
R = Reserved 1. Writing a 0 clears SBSW.
Figure 18-6. SIM Break Status Register (SBSR)
Address:
$FE03
Bit 7654321Bit 0
Read:
BCFE RRRRRRR
Write:
Reset: 0
R
= Reserved
Figure 18-7. SIM Break Flag Control Register (SBFCR)